Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCASES 2004: Washington, DC, USA
- Mary Jane Irwin, Wei Zhao, Luciano Lavagno, Scott A. Mahlke:
Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004. ACM 2004, ISBN 1-58113-890-3 - Kees A. Vissers:
Programming models and architectures for FPGA platforms. 1
Memory systems
- Ali El-Haj-Mahmoud, Eric Rotenberg:
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. 2-13 - Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy:
Dynamic on-chip memory management for chip multiprocessors. 14-23 - Ken W. Batcher, Robert A. Walker:
Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. 24-34 - Jayaprakash Pisharath, Alok N. Choudhary, Mahmut T. Kandemir:
Reducing energy consumption of queries in memory-resident database systems. 35-45
Application specific processors
- Binu K. Mathew, Al Davis, Michael A. Parker:
A low power architecture for embedded perception. 46-56 - Timothy Sherwood
, Mark Oskin, Brad Calder:
Balancing design options with Sherpa. 57-68 - Pan Yu, Tulika Mitra:
Scalable custom instructions identification for instruction-set extensible processors. 69-78 - Jesus Garcia, Mark G. Arnold, Leonidas G. Bleris, Mayuresh V. Kothare:
LNS architectures for embedded model predictive control processors. 79-84
Low power SOCs and NOCs
- Giovanni Beltrame, Gianluca Palermo, Donatella Sciuto, Cristina Silvano:
Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs. 85-92 - Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan:
Disk drive energy optimization for audio-video applications. 93-103 - Noel Eisley, Li-Shiuan Peh:
High-level power analysis for on-chip networks. 104-115 - Shaoxiong Hua, Gang Qu:
Energy-efficient dual-voltage soft real-time system with (m, k)-firm deadline guarantee. 116-123
Low power processors
- Bramha Allu, Wei Zhang:
Static next sub-bank prediction for drowsy instruction cache. 124-131 - Montserrat Ros, Peter Sutton:
A hamming distance based VLIW/EPIC code compression technique. 132-139 - Linwei Niu, Gang Quan:
Reducing both dynamic and leakage energy consumption for hard real-time systems. 140-148 - Wei Zhang, Bramha Allu:
Loop-based leakage control for branch predictors. 149-155 - John Cornish:
Balanced energy optimization. 156
Compiler analysis and optimization
- Ramakrishnan Venkitaraman, Gopal Gupta:
Static program analysis of embedded executable assembly code. 157-166 - Vasanth Asokan, Alexander G. Dean:
Providing time- and space- efficient procedure calls for asynchronous software thread integration. 167-178 - Klaus Schneider, Jens Brandt, Tobias Schüle:
Causality analysis of synchronous programs with delayed actions. 179-189 - Meilin Liu, Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha:
General loop fusion technique for nested loops considering timing and code size. 190-201
Co-design and synthesis
- David Berner, Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla:
Modular design through component abstraction. 202-211 - Valentina Salapura, Christos J. Georgiou, Indira Nair:
An efficient system-on-a-chip design methodology for networking applications. 212-219 - Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Translating affine nested-loop programs to process networks. 220-229 - Mary Kiemb, Kiyoung Choi:
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. 230-237
Memory optimization
- Steve Carr, Philip H. Sweany:
Automatic data partitioning for the agere payload plus network processor. 238-247 - Sven Verdoolaege, Rachid Seghir, Kristof Beyls, Vincent Loechner, Maurice Bruynooghe:
Analytical computation of Ehrhart polynomials: enabling more compiler analyses and optimizations. 248-258 - Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri:
A post-compiler approach to scratchpad mapping of code. 259-267 - Christophe Guillon, Fabrice Rastello, Thierry Bidault, Florent Bouchez:
Procedure placement using temporal-ordering information: dealing with code size expansion. 268-279
Reliability and security
- Surupa Biswas, Matthew S. Simpson, Rajeev Barua:
Memory overflow protection for embedded systems using run-time checks, reuse and compression. 280-291 - Xiaotong Zhuang, Tao Zhang, Hsien-Hsin S. Lee, Santosh Pande:
Hardware assisted control flow obfuscation for embedded processors. 292-302 - Yusuke Matsuoka, Patrick Schaumont, Kris Tiri, Ingrid Verbauwhede:
Java cryptography on KVM and its performance and security optimization using HW/SW co-design techniques. 303-311
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-16 20:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
