41st DAC 2004: San Diego, CA, USA

Refine list

showing all ?? records

Panel

Hot Leakage

Clock Routing and Buffering

Tools and Strategies for Dynamic Verification

Timing-Driven System Synthesis

Reliable System-on-a-chip Design in the Nanometer Era

Panel

Power Modeling and Optimization for Embedded Systems

Performance Evaluation and Run Time Support

Advances in Analog Circuit and Layout Synthesis

Power Grid Design and Analysis Techniques

Panel

Methods for A Priori Feasible Layout Generation

Abstraction Techniques for Functional Verification

Memory and Network Optimization in Embedded Designs

Business Day Session

The Future of Timing Closure

Panel

Design Space Exploration and Scheduling for Embedded Software

Advances in Accelerated Simulation

Design for Manufacturing

Statistical Timing Analysis

Panel

New Ideas in Placement

Model Order Reduction and Variational Techniques for Parasitic Analysis

Compilation Techniques for Embedded Applications

Platform-based System Design

Innovations in Logic Synthesis

Yield Estimation and Optimization

High-level Techniques for Signal Processing

Advanced Test Solutions

Panel

Advances in Boolean Analysis Techniques

Panel

Power Optimization for Real-Time and Media-Rich Embedded Systems

Latency Tolerance and Asynchronous Design

New Technologies in System Design

BioMEMS

Panel

Floorplanning

Issues in Timing Analysis

ISSCC Highlights

Multiprocessor SoC MPSoC Solutions/Nightmare

Timing Issues in Placement

Design Methodologies for ASIPs

FPGA-Based Systems

Security as a New Dimension in Embedded System Design

Leakage Power Optimization

Interconnect Extraction

New Frontiers in Logic Synthesis

Numerical Techniques for Simulation

Energy and Thermal-Aware Design

Noise-Tolerant Design and Analysis Techniques

New Tools and Methods for Future Embedded SoC

New Scan-Based Test Techniques

CAD for Reconfigurable Computing

a service of  Schloss Dagstuhl - Leibniz Center for Informatics