Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDFT 1994: Montréal, Quebec, Canada
- The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 17-19, 1994, Montréal, Quebec, Canada, Proceedings. IEEE Computer Society 1994, ISBN 0-8186-6307-3
Fault Tolerant Architectures
- Yinan N. Shen, Hannu H. Kari, Sungsoo Kim, Fabrizio Lombardi:
Scheduling Policies for Fault Tolerance in a VLSI Processor. DFT 1994: 1-9 - Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
A CMOS Fault Tolerant Architecture for Swith-Level Faults. DFT 1994: 10-18 - M. B. Alhaji-Hussaini, R. Mike Lea:
A Defect and Fault Tolerant Interconnection Network Strategy for WASP Devices. DFT 1994: 19-27 - Stephanie R. Goldberg, Shambhu J. Upadhyaya:
Implementation of a Gracefully Degradable Binary Tree in Programmable. DFT 1994: 28-36 - Luigi Dadda, Vincenzo Piuri:
Fault-Tolerant Modular Convolves. DFT 1994: 37-45
Testable Architectures
- Carles Ferrer, D. Dateo, Joan Oliver, Antonio Rubio, M. Rullán:
An Approach to the Development of a IDDQ Testable Cell Library. DFT 1994: 46-54 - Zaifu Zhang, Robert D. McLeod, Witold Pedrycz:
Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing. DFT 1994: 55-64 - Andrew J. Bishop, André Ivanov:
On the Testability of CMOS Feedback Amplifiers. 65-73 - Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao:
Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor Arrays. DFT 1994: 74-82
Yield and Defect Model
- Charles H. Stapper, A. J. Rideout:
On Fractal Yield Models: A Statistical Paradox. DFT 1994: 83-87 - Gerard A. Allan, Anthony J. Walton:
Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies. DFT 1994: 88-96 - Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns:
The Effect of Wire Length Minimization on Yield. DFT 1994: 97-105
Invited Speaker
- Glenn H. Chapman:
Laser Processes for Defect Correction in Large Area VLSI Systems. DFT 1994: 106-114
Self-Checking and Coding Techniques
- Fabio Salice, Mariagiovanna Sami, Donatella Sciuto:
Synthesis of Multi-level Self-Checking Logic. DFT 1994: 115-123 - T. Bogue, Helmut Jürgensen, Michael Gössel:
Design of Cover Circuits for Monitoring the Output of a MISA. DFT 1994: 124-132 - Cecilia Metra, Michele Favalli, Bruno Riccò:
CMOS Self Checking Circuits with Faulty Sequential Functional Block. DFT 1994: 133-141 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n CMOS Checkers. DFT 1994: 142-150 - Sihai Xiao, Xiaofa Shi, Guilang Feng, T. R. N. Rao:
Some Results on Improving the Code Length of SbEC-DED Codes. DFT 1994: 151-158
Fault-Tolerant Techniques
- Yuang-Ming Hsu, Earl E. Swartzlander Jr.:
Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. DFT 1994: 159-167 - Jie-Chung Lo:
A Fault-Tolerant Associative Approach to On-Line Memory Repair. DFT 1994: 168-176 - Hideo Ito, Takashi Yagi:
Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT 1994: 177-184 - Rachid Kermouche, Yvon Savaria:
Defect and Fault Tolerant Scan Chains. DFT 1994: 185-193
Reconfiguration Techniques
- Anuj Chandra, Rami G. Melhem:
Reconfiguration in 3D Meshes. DFT 1994: 194-202 - Tong Liu, Fabrizio Lombardi:
On Soft Switch Programming for Reconfigurable Array Systems. DFT 1994: 203-211 - Susumu Horiguchi, Issei Numata:
A Self-Reconfiguration Architecture for Mesh Arrays. DFT 1994: 212-220 - Weiping Shi:
A General Method to Design and Reconfigure Loop-Based Linear Arrays. DFT 1994: 221-229
Yield Enhancement
- Brenda S. Cantell, Randall S. Collica, José G. Ramírez:
Statistical analysis of Particle/Defect Data Experiments Using Poisson and Logistic Regression. DFT 1994: 230-238 - Zhan Chen, Israel Koren:
A Yield Study of VLSI Adders. DFT 1994: 239-245 - Kiyoshi Mori, Nam T. Nguyen, Dewey Keeton, Ross Burns:
Yield Enhancement with Particle Defects Reduction. DFT 1994: 246-253
Testing Techniques
- Franco Fummi, Donatella Sciuto, Micaela Serra:
Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method. DFT 1994: 254-262 - A. P. Casimiro, Fernando M. Gonçalves, João Paulo Teixeira, Marcelino B. Santos:
On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. DFT 1994: 263-270 - Régis Leveugle, Raphaël Rochet, Gabriele Saucier:
Alternative Approaches to Fault Detection in FSMs. DFT 1994: 271-279 - Claude Thibeault:
Using Fourier Analysis to Enhance IC Testability. DFT 1994: 280-298
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-16 20:18 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
