DSD 2014: Verona, Italy

Reconfigurable Computing 1 (RC1)

Flexible Digital Radio (FDR)

Reconfigurable Computing 2 (RC2)

Reconfigurable Computing 3 (RC3)

High Performance Video Processing (HPVP)

Dependability, Testing and Fault Tolerance in Digital Systems

Power Design (PD)

Synchronisation (SYNC)

MultiProcessor System On Chip (MPSOC)

Architectures and Hardware for Security Applications 1 (AHSA1)

European Projects in Digital System Design 1 (EPDSD1)

European Projects in Digital System Design 2 (EPDSD2)

Application Specific Pocessor 1 (ASP1)

Design of Heterogeneous Cyber-Physical Systems (DHCPS)

Application Specific Pocessor 2 (ASP2)

Mixed Criticality System Design, Implementation and Analysis

Dependability, Testing and Fault Tolerance in Digital Systems

Architecture Optimization (ARCH)

Emerging Technologies and Circuit Synthesis (ETCS)

Architectures and Hardware for Security Applications 2 (AHSA2)

Mixed Criticality System Design, Implementation and Analysis

Logic Synthesis 1 (LS1)

Logic Synthesis 2 (LS2)

Logic Synthesis 3 (LS3)

Application Specific Processor 3 (ASP3)

Verification and Reliable Design (VRD)

Network on Chip (NoC)

Architectures and Hardware for Security Applications 3 (AHSA3)

Real-Time Custom Computing (RTCC)

Dependability, Testing and Fault Tolerance in Digital Systems

Synthesis (SYNT)

Multiprocessing Partitioning and Scheduling (MPS)

Poster Papers

Systems through Co-simulation687

maintained by Schloss Dagstuhl LZI at University of Trier