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ORCIDHLDVT 2006: Monterey, CA, USA
- Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, Monterey, CA, USA, Nov 9-10, 2006. IEEE Computer Society 2006, ISBN 1-4244-0679-X
Test Case Generation I
- Kevin D. Rich, Robert Shaw, Shankar G. Govindaraju, David Dobrikin:
DVGen: Increasing Coverage by Automatically Combining Test Specifications. 3-10 - Hsiou-Wen Hsueh, Kerstin Eder:
Test Directive Generation for Functional Coverage Closure Using Inductive Logic Programming. 11-18 - Amer Samarah, Ali Habibi, Sofiène Tahar, Nawwaf N. Kharma:
Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm. 19-26
Special Session I
- Stergios Stergiou, Jawahar Jain:
Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. 29-36 - Wolfgang Meyer:
Trends in Test: Challenges and Techniques. 37 - Kei-Yong Khoo:
Formal Verifications in Modern Chip Designs. 38
Testing and Design for Testability
- José M. Fernandes, Marcelino B. Santos
, Arlindo L. Oliveira, João Paulo Cacho Teixeira:
DFT and Probabilistic Testability Analysis at RTL. 41-47 - Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). 48-54 - Shireesh Verma, Patricia S. Lee, Ian G. Harris:
Error Detection Using Model Checking vs. Simulation. 55-58
Assertions and Transactions
- Íñigo Ugarte, Pablo Sanchez:
Assertion-based Verification of Behavioral Descriptions with Non-linear Solver. 61-68 - Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. 69-76 - Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Specification Language for Transaction Level Assertions. 77-84 - Nicola Bombieri, Franco Fummi:
On the Automatic Transactor Generation for TLM-based Design Flows. 85-92
Test Case Generation II
- Michal Rimon, Yossi Lichtenstein, Allon Adir, Itai Jaeger, Michael Vinov, S. Johnson, D. Jani:
Addressing Test Generation Challenges for Configurable Processor Verification. 95-101 - Allon Adir, Laurent Fournier, Yoav Katz, Anatoly Koyfman:
DeepTrans - Extending the Model-based Approach to Functional Verification of Address Translation Mechanisms. 102-110 - Boris Gutkovich, Anna Moss:
CP with Architectural State Lookup for Functional Test Generation. 111-118 - Avishay Maman, Sharon Goldschlager, Hillel Miller, David Bell, Rob Slater, Oded Ben-Moshe, Nissan Levi, Hagit Gilboa:
Reusable On-Chip System Level Verification for Simulation Emulation and Silicon. 119-126
Transformation-based Verification
- Samar Abdi, Daniel Gajski:
Transaction Routing and its Verification by Correct Model Transformations. 129-136 - Vivekananda M. Ve. Andersen, Jacob A. Abraham:
Taming the Complexity of STE-based Design Verification Using Program Slicing. 137-142 - Ajit Dingankar, Deepak Mathaikutty, Sreekumar V. Kodakara, Sandeep K. Shukla, David J. Lilja:
MMV: Metamodeling Based Microprocessor Valiation Environment. 143-148
Special Session II
- Valeria Bertacco:
Distance-Guided Hybrid Verification with GUIDO. 151 - Alan J. Hu:
EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation. 151-152 - Jason Baumgartner:
Semi-Formal Verification at IBM. 152
SAT and Equivalence Verification
- Vijay Durairaj, Priyank Kalla:
Guiding CNF-SAT Search by Analyzing Constraint-Variable Dependencies and Clause Lengths. 155-161 - Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Equivalence Checking with Rule-Based Equivalence Propagation and High-Level Synthesis. 162-169 - In-Ho Moon, Per Bjesse, Carl Pixley:
Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces. 170-175 - Feng Lu, Kwang-Ting Cheng:
IChecker: An Efficient Checker for Inductive Invariants. 176-180
Panel
- Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley:
Panel: Assertion-Based Verification -What's the Big Deal? 183
System Level View and Modeling
- Eric Cheung, Piyush Satapathy, Vi Pham, Harry Hsieh, Xi Chen:
Runtime Deadlock Analysis of SystemC Designs. 187-194 - Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Magdy S. Abadir:
Extracting a simplified view of design functionality via vector simulation. 195-202 - Sami Taktak, Emmanuelle Encrenaz, Jean Lou Desbarbieux:
A Tool for Automatic Detection of Deadlock in Wormhole Networks on Chip. 203-210 - Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, Jean-Pierre Talpin:
Polychronous Methodology For System Design: A True Concurrency Approach. 211-214
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