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ORCID5. IDT 2010: Abu Dhabi, UAE
- Yervant Zorian, Imtinan Elahi, André Ivanov, Ashraf Salem:
5th International Design and Test Workshop, IDT 2010, Abu Dhabi, UAE, 14-15 December 2010. IEEE 2010, ISBN 978-1-61284-291-2 - Romany Sameer, Ahmed Nader Mohieldin
, Haitham Eissa:
An automated design methodology for stress avoidance in analog & mixed signal designs. 3-7 - Bassel Soudan:
Improving timing characteristics through Semi-Random Net Reordering. 8-12 - Rami F. Salem, Abdelrahman ElMously, Haitham Eissa, Mohamed Dessouky, Mohab H. Anis:
A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs. 13-17 - Sohaib Majzoub:
Voltage island design in multi-core SIMD processors. 18-23 - Lamiaa A. Elazm, Magdy A. El-Moursy, Hamed Elsimary, Moawad I. Dessouky, Farid Shawki:
High speed low power composite field SBOX. 24-27 - Abdallah Y. Alma'aitah, Zine-Eddine Abid:
Area efficient-high throughput sub-pipelined design of the AES in CMOS 180nm. 31-36 - Brahim Attia, Wissem Chouchene, Abdelkrim Zitouni, Abid Nourdin, Rached Tourki:
Design and implementation of low latency network interface for network on chip. 37-42 - Bouthaina Damak, Mouna Baklouti, Mohamed Abid:
Soft-core reduction methodology for SIMD architecture: OPENRISC case study. 43-48 - Nor Zaidi Haron, Said Hamdioui, Zaiyan Ahyadi:
ECC design for fault-tolerant crossbar memories: A case study. 61-66 - Walid Ibrahim, Valeriu Beiu, Azam Beg:
On NOR-2 von Neumann multiplexing. 67-72 - Syed Askari, Mehrdad Nourani:
A design for reliability methodology based on selective overdesign. 73-77 - Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Eman AlQuraishi:
Cost-free low-power test in compression-based reconfigurable scan designs. 78-82 - Mariem Turki, Mohamed Abid, Zied Marrakchi, Habib Mehrez:
Routability driven placement for mesh-based FPGA architecture. 85-90 - Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu:
Reconfigurable low-power Concurrent Error Detection in logic circuits. 91-96 - Ismail Ktata, Fakhreddine Ghaffari, Bertrand Granado, Mohamed Abid:
Prediction performance method for dynamic task scheduling, case study: the OLLAF Architecture. 97-102 - Mona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem:
A novel conflict directed jumping algorithm for hardware-based SAT solvers. 103-108 - Hamzah A. Abdel-Aziz, Mostafa M. Abdel-Aziz, Amr G. Wassal, Ahmed A. Abou-Auf:
Worst-case test vectors generation using genetic algorithms for the detection of total-dose induced leakage current failures. 117-121 - Junxia Ma, Mohammad Tehranipoor, Ozgur Sinanoglu, Sobeeh Almukhaizim:
Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG. 122-127 - Ad J. van de Goor, Said Hamdioui:
MBIST architecture framework based on orthogonal constructs. 128-133 - Sandra Irobi, Zaid Al-Ars, Michel Renovell:
Parasitic memory effect in CMOS SRAMs. 134-139 - Mathias Soeken, Robert Wille, Rolf Drechsler:
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. 143-148 - Hongyan Zhang, Robert Wille, Rolf Drechsler:
SAT-based ATPG for reversible circuits. 149-154 - Laiq Hasan, Zaid Al-Ars, Mottaqiallah Taouil, Koen Bertels:
Performance and bandwidth optimization for biological sequence alignment. 155-160 - Samah Hassan, Mohamed Taher, Ayman M. Wahba:
Mapping SMV models to event-B models. 161-166
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