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ORCID19th ISQED 2018: Santa Clara, California, USA
- 19th International Symposium on Quality Electronic Design, ISQED 2018, Santa Clara, CA, USA, March 13-14, 2018. IEEE 2018, ISBN 978-1-5386-1214-9
Keynote
- Kerry Bernstein:
Murphy was an optimist: Embracing asymmetry in electronics.
Session 1A: Design Verification and Test
- Bin Lin, Kai Cong, Zhenkun Yang, Zhi-gang Liao, Tao Zhan, Christopher Havlicek, Fei Xie:
Concolic testing of SystemC designs. 1-7 - Aydin Dirican, Cagatay Ozmen, Martin Margala
:
A droop measurement built-in self-test circuit for digital low-dropout regulators. 8-13 - Pavan Kumar Javvaji, Basim Shanyour, Spyros Tragoudas:
Test set identification for improved delay defect coverage in the presence of statistical delays. 14-19 - Patrick Girard:
Power-aware testing in the Era of IoT. 17-20 - Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono:
Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT. 20-24
Session 1B: System-level Design and Methodologies (SDM)
- Amin Jadidi, Mohammad Arjomand, Mahmut T. Kandemir, Chita R. Das:
Hybrid-comp: A criticality-aware compressed last-level cache. 25-30 - Juyeon Kim, Taewhan Kim:
Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network. 31-36 - Jiacong He, Joseph Callenes-Sloan:
Optimizing energy in a DRAM based hybrid cache. 37-42 - Mohsen Imani, Daniel Peroni, Tajana Rosing:
Program acceleration using nearest distance associative search. 43-48
Session 1C: Emerging Logic and Memory Technologies in IoT and Neuromorphic Architectures
- Arman Roohi, Ramtin Zand, Ronald F. DeMara:
Synthesis of normally-off boolean circuits: An evolutionary optimization approach utilizing spintronic devices. 49-54 - Joonseop Sim, Mohsen Imani, Woojin Choi, Yeseong Kim, Tajana Rosing:
LUPIS: Latch-up based ultra efficient processing in-memory system. 55-60 - Zoha Pajouhi:
Energy efficient neuromorphic processing using spintronic memristive device with dedicated synaptic and neuron terminology. 61-68 - Sagarvarma Sayyaparaju, Sherif Amer, Garrett S. Rose:
A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems. 69-74
Session 2A: Automated Analog and Digital Circuit Optimization
- Yu-Cheng Chiang, Shr-Cheng Tsai, Rung-Bin Lin:
Recognition of regular layout structures. 75-81 - Pradeep Kumar Chawda:
A simplified methodology for complex analog module layout generation. 82-87 - Shinichi Nishizawa, Hidetoshi Onodera:
Process variation aware D-Flip-Flop design using regression analysis. 88-93 - Joohan Kim, Taewhan Kim:
Clock buffer and flip-flop co-optimization for reducing peak current noise. 94-99 - Tuotian Liao, Lihong Zhang:
Parasitic-aware gm/ID-based many-objective analog/RF circuit sizing. 100-105
Session 2B: System-level Design and Methodologies (SDM)
- Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. 106-111 - Ahmad Mansour, Ahmed El-Naggar, Bassma Al-Abassy, Mostafa Khamis, Ahmed Shalaby:
A 4-PAM interconnect in network-on-chip for high-throughput and latency-sensitive applications. 112-118 - Sara Karimi, Jelena Trajkovic:
Comparative study and prediction modeling of photonic ring Network on Chip architectures. 119-126 - Milena Vratonjic, Harmander Singh, Gautam Kumar, Roumi Mohamed, Ashish Bajaj, Ken Gainey:
Power and performance aware memory-controller voting mechanism. 127-130 - Jindun Dai, Renjie Li, Xin Jiang, Takahiro Watanabe:
PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs. 131-137
Session 2C: Poster Papers
- Boris Vaisband, Adeel Ahmad Bajwa, Subramanian S. Iyer:
Network on interconnect fabric. 138-143 - Jihyun Ryoo, Meena Arunachalam, Rahul Khanna, Mahmut T. Kandemir:
Efficient K nearest neighbor algorithm implementations for throughput-oriented architectures. 144-150 - Jheng-Yi Chen, Ming-Yu Chang, Shi-Hao Chen, Jia-Wei Lee, Meng-Hsueh Chiang:
Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. 151-155 - Frederico Pratas, Thomas Dedes, Andrew Webber, Majid Bemanian, Itai Yarom:
Measuring the effectiveness of ISO26262 compliant self test library. 156-161 - Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan:
An online framework for diagnosis of multiple defects in scan chains. 162-168 - Chun-Xun Lin, Tsung-Wei Huang, Martin D. F. Wong:
Routing at compile time. 169-175 - Wenkai Guan, Milad Ghorbani Moghaddam, Cristinel Ababei:
Uncertainty aware mapping of embedded systems for reliability, performance, and energy. 176-183 - Albert Ciprut, Eby G. Friedman:
On the write energy of non-volatile resistive crossbar arrays with selectors. 184-188 - Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu:
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects. 189-195 - Victor Huang, Chenyun Pan, Azad Naeemi:
Generic system-level modeling and optimization for beyond CMOS device applications. 196-200 - Huan Wang, Jean-François Millithaler, Ronald W. Knepper, Martin Margala:
Terahertz travelling wave amplifier design using Ballistic Deflection Transistor. 201-206 - Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Reliable memory PUF design for low-power applications. 207-213 - Mahdi Elghazali, Manoj Sachdev, Ajoy Opal:
An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. 214-220 - Ujas Patel, Sai Nimmalapudi, Harvey Stiegler, Andrew Marshall, Keith Jarreau:
Enhancing circuit operation using analog floating gates. 221-226 - Pradeep Kumar Chawda, Shrikrishna Srinivasan:
An automated flow for design validation of switched mode power supply. 227-231 - Sidhartha Sankar Rout, Hemanta Kumar Mondal, Rohan Juneja, Sri Harsha Gade, Sujay Deb:
Dynamic NoC platform for varied application needs. 232-237
Session 3A.1: Design Verification and Test
- Ruslan Dautov, Sergey G. Mosin:
A technique to aggregate classes of analog fault diagnostic data based on association rule mining. 238-243 - Mami Miyamoto, Kiyoharu Hamaguchi:
Extracting hardware assertions including word-level relations over multiple clock cycles. 244-250
Session 3A.2: Automated Analog and Digital Circuit Optimization
- Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
A study on NBTI-induced delay degradation considering stress frequency dependence. 251-256 - Mohammed Fakhruddin, Kuok-Khian Lo, James Karp, Michael J. Hart, Min-Hsing P. Chen:
Verification methodology to guarantee low routing resistance to well taps. 257-261
Session 3B: High Performance / Low Power Logic Design
- Przemyslaw Mroszczyk, Vasilis F. Pavlidis:
Ultra-low swing CMOS transceiver for 2.5-D integrated systems. 262-267 - Arif Siddiqi, Navneet Jain, Mahbub Rashed:
Back-bias generator for post-fabrication threshold voltage tuning applications in 22nm FD-SOI process. 268-273 - Vivek Nautiyal, Nishant Nukala, Fakhruddin Ali Bohra, Sagar Dwivedi, Jitendra Dasani, Satinderjit Singh, Gaurav Singla, Martin Kinkade:
Logic-based row redundancy technique designed in 7nm FinFET technology for embedded SRAMs. 274-279 - Hassan Afzali-Kusha, Alireza Shafaei, Massoud Pedram:
A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell. 280-285
Session 3C: IoT and Smart Sensors
- Gaorong Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang:
New AC resistance calculation of printed spiral coils for wireless power transfer. 286-289 - Pradeep Kumar Chawda:
An automated design flow for synthesis of optimal multi-layer multi-shape PCB coils for inductive sensing applications. 290-295 - Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, Mircea R. Stan:
When "things" get older: Exploring circuit aging in IoT applications. 296-301
Session 4A.1: Design Technology Co-Optimization
Session 4A.2: Machine Learning on Conventional and Emerging Platforms
- Jialing Li, Kangjun Bai, Lingjia Liu, Yang Yi:
A deep learning based approach for analog hardware implementation of delayed feedback reservoir computing system. 308-313 - Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, Jingtong Hu, Yanzhi Wang:
An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing. 314-321 - Kangjun Bai, Yang Yi Bradley:
A path to energy-efficient spiking delayed feedback reservoir computing system for brain-inspired neuromorphic processors. 322-328
Session 4B: High Performance / Low Power Logic Design
- Kamlesh Singh, Hailong Jiao, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez:
Low power latch based design with smart retiming. 329-334 - Cong Ma, David J. Lilja:
Parallel implementation of finite state machines for reducing the latency of stochastic computing. 335-340 - Divya Akella Kamakshi, Xinfei Guo, Harsh N. Patel, Mircea R. Stan, Benton H. Calhoun:
A post-silicon hold time closure technique using data-path tunable-buffers for variation-tolerance in sub-threshold designs. 341-346 - Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
A low-power configurable adder for approximate applications. 347-352
Session 4C: IoT & Smart Sensors
- Paul C.-P. Paul, Pei-Yu Chiang, Der-Cherng Tarng, Chih-Yu Yang:
Mathematical derivation, circuits design and clinical experiments of measuring blood flow volume (BFV) at arteriovenous fistula (AVF) of hemodialysis (HD) patients using a newly-developed photoplethysmography (PPG) sensor. 353-356 - Linxi Dong, Haonan Wang, Gaofeng Wang, Weimin Qiu:
A wireless multifunctional monitoring system of tower body running state based on MEMS acceleration sensor. 357-363 - Anupriya Prasad, Pradeep Chawda:
Power management factors and techniques for IoT design devices. 364-369 - Axel Jantsch, Arman Anzanpour, Hedyeh A. Kholerdi, Iman Azimi, Lydia C. Siafara, Amir M. Rahmani, Nima Taherinejad, Pasi Liljeberg, Nikil D. Dutt:
Hierarchical dynamic goal management for IoT systems. 370-375
Session 5A: Machine Learning on Conventional and Emerging Platforms
- Bingzhe Li, M. Hassan Najafi, Bo Yuan, David J. Lilja:
Quantized neural networks with new stochastic multipliers. 376-382 - Raghav Mehta, Yuyang Huang, Mingxi Cheng, Shrey Bagga, Nishant Mathur, Ji Li, Jeffrey Draper, Shahin Nazarian:
High performance training of deep neural networks using pipelined hardware acceleration and distributed memory. 383-388 - Mohsen Imani, Pushen Wang, Tajana Rosing:
Deep neural network acceleration framework under hardware uncertainty. 389-394 - Mahdi Nazemi, Amir Erfan Eshratifar, Massoud Pedram:
A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA. 395-400
Session 5B: Hardware Security: PUF, Obfuscation, and Trojan Detection
- Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Kevin A. Kwiat, Qiaoyan Yu:
Securing FPGA-based obsolete component replacement for legacy systems. 401-406 - Sheikh Ariful Islam, Srinivas Katkoori:
High-level synthesis of key based obfuscated RTL datapaths. 407-412 - Anthony Mattar El Raachini, Hussein Alawieh, Adam Issa, Zainab Swaidan, Rouwaida Kanj, Ali Chehab, Mazen A. R. Saghir:
Double error cellular automata-based error correction with skip-mode compact syndrome coding for resilient PUF design. 413-418 - Ahmet Turan Erozan, Mohammad Saber Golanbari, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
Design and evaluation of physical unclonable function for inorganic printed electronics. 419-424
Session 5C: Demystifying Self-driving Cars
- Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li:
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. 425-431 - Mihir Mody, Kumar Desappan, Pramod Swami, Manu Mathew, Soyeb Nagori:
Low cost and power CNN/deep learning solution for automated driving. 432-436 - Xiaowei Xu, Tianchen Wang, Qing Lu, Yiyu Shi:
Resource constrained cellular neural networks for real-time obstacle detection using FPGAs. 437-440
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