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ORCID10th MCSoC 2016: Lyon, France
- 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSOC 2016, Lyon, France, September 21-23, 2016. IEEE Computer Society 2016, ISBN 978-1-5090-3531-1
Session 1: Architectures
- Wissem Chouchene, Rabie Ben Atitallah, Jean-Luc Dekeyser:
AFFORDe: Automatic Allocation and Floorplanning for SPMD Architecture. 1-7 - Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment. 8-14 - Sarat Yoowattana, Tomohiro Yoneda:
Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance. 15-22 - Alessandro Siino, Francesco Barchi, Sergio Davies
, Gianvito Urgese, Andrea Acquaviva:
Data and Commands Communication Protocol for Neuromorphic Platform Configuration. 23-30
Session 2: Interconnect Networks (NoCs) I
- Masoud Oveis Gharan, Gul N. Khan:
Adaptive VC Organization and Arbitration for Efficient NoC Design. 31-38 - Asma Benmessaoud Gabis, Marc Sevaux, Pierre Bomel, Mouloud Koudil, Karima Benatchba:
Heuristic Based Routing Algorithm for Network on Chip. 39-45 - Ye Liu, Hiroshi Sasaki, Shinpei Kato, Masato Edahiro:
A Scalability Analysis of Many Cores and On-Chip Mesh Networks on the TILE-Gx Platform. 46-52
Session 3: Energy Efficiency
- Maximilian Gotzinger, Amir M. Rahmani, Martin Pongratz, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen:
The Role of Self-Awareness and Hierarchical Agents in Resource Management for Many-Core Systems. 53-60 - Mohamed Lamine Karaoui, Pierre-Yves Peneau, Quentin L. Meunier, Franck Wajsbürt, Alain Greiner:
Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures. 61-68 - Lau Phi Tuong, Keiji Kimura:
2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores. 69-76
Session 4: Benchmarks
- Romain Saussard, Boubker Bouzid, Marius Vasiliu, Roger Reynaud:
A Robust Methodology for Performance Analysis on Hybrid Embedded Multicore Architectures. 77-84 - Lin Li, Markus Fussenegger, Gordon Cichon:
A Data Locality and Memory Contention Analysis Method in Embedded NUMA Multi-core Systems. 85-92 - Julien Worms, Sid Ahmed Ali Touati:
Going beyond Mean and Median Programs Performances. 93-100 - Malgorzata Michalska, Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
High-Precision Performance Estimation of Dynamic Dataflow Programs. 101-108
Session 5: Interconnect Networks (NoCs) II
- Stephanie Friederich, Marco Neber, Jürgen Becker:
Power Management Controller for Online Power Saving in Network-on-Chips. 109-116 - Hamidreza Ahmadian, Roman Obermaisser, Mohammed Abuteir:
Time-Triggered and Rate-Constrained On-chip Communication in Mixed-Criticality Systems. 117-124 - Steve Kerrison, David May, Kerstin Eder:
A Benes Based NoC Switching Architecture for Mixed Criticality Embedded Systems. 125-132
Session 6: Reconfigurable and Parallel Computing
- Hiliwi Leake Kidane, El-Bay Bourennane, Gilberto Ochoa-Ruiz:
NoC Based Virtualized Accelerators for Cloud Computing. 133-137 - Kazushi Yamashina, Hitomi Kimura, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota:
cReComp: Automated Design Tool for ROS-Compliant FPGA Component. 138-145 - Dihia Belkacemi, Youcef Bouchebaba, Mehammed Daoui, Mustapha Lalam:
Network on Chip and Parallel Computing in Embedded Systems. 146-152
Session 7: Emerging Technologies and Paradigms
- Feiyang Liu, Haibo Zhang, Yawen Chen, Zhiyi Huang, Huaxi Gu:
Dynamic Ring-Based Multicast with Wavelength Reuse for Optical Network on Chips. 153-160 - Melika Tinati, Somayyeh Koohi, Shaahin Hessabi:
Impact of on-chip power distribution on Temperature-Induced Faults in Optical NoCs. 161-168
Session 8: Design I
- Hiroshi Saito, Masashi Imai, Tomohiro Yoneda:
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. 169-176 - Keiji Kimura, Gakuho Taguchi, Hironori Kasahara:
Accelerating Multicore Architecture Simulation Using Application Profile. 177-184 - Abdoulaye Gamatié, Roman Ursu, Manuel Selva, Gilles Sassatelli:
Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural Networks. 185-192
Session 9: Design II
- Kristoffer Robin Stokke, Håkon Kvale Stensland, Pål Halvorsen, Carsten Griwodz:
High-Precision Power Modelling of the Tegra K1 Variable SMP Processor Architecture. 193-200 - Anastasiia Butko, Florent Bruguier, Abdoulaye Gamatié, Gilles Sassatelli, David Novo, Lionel Torres, Michel Robert:
Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration. 201-208 - Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Steven Derrien:
Communication-Based Power Modelling for Heterogeneous Multiprocessor Architectures. 209-216 - Malgorzata Michalska, Nicolas Zufferey, Endri Bezati, Marco Mattavelli:
Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures. 217-224
Session 10: Interconnect Networks (NoCs) III
- Yves Durand, Christian Bernard, Fabien Clermidy:
Distributed Dynamic Rate Adaptation on a Network on Chip with Traffic Distortion. 225-232 - Zoran A. Salcic, Muhammad Nadeem, HeeJong Park, Jürgen Teich:
Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor. 233-240 - José V. Escamilla, Mario R. Casu, José Flich:
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. 241-248
Session 11: Programming
- Loïc Cudennec, Safae Dahmani, Guy Gogniat, Cédric Maignan, Martha Johanna Sepúlveda:
Network Contention-Aware Method to Evaluate Data Coherency Protocols within a Compilation Toolchain. 249-256 - Joo On Ooi, Fawnizu Azmadi B. Hussin, Nordin Zakaria:
Dual-Engine Cross-ISA DBTO Technique Utilising MultiThreaded Support for Multicore Processor System. 257-264 - Fernando Akira Endo, Damien Couroussé, Henri-Pierre Charles:
Pushing the Limits of Online Auto-Tuning: Machine Code Optimization in Short-Running Kernels. 265-272
Special Session on Programming Models and Methods for Heterogeneous Parallel Embedded Systems
- Lars Middendorf, Christian Haubelt:
Supporting Static Binding in Stream Rewriting for Heterogeneous Many-Core Architectures. 273-280 - Andres Goens, Robert Khasanov, Jerónimo Castrillón, Simon Polstra, Andy D. Pimentel:
Why Comparing System-Level MPSoC Mapping Approaches is Difficult: A Case Study. 281-288 - Simone Casale Brunet, Endri Bezati, Marco Mattavelli:
Programming Models and Methods for Heterogeneous Parallel Embedded Systems. 289-296
Special Session on Approaches and Frameworks for Predictable Multi-core Processing
- Eugene Yip, Alain Girault, Partha S. Roop, Morteza Biglari-Abhari:
The ForeC Synchronous Deterministic Parallel Programming Language for Multicores. 297-304 - Connor Imes, David H. K. Kim, Martina Maggio, Henry Hoffmann:
Portable Multicore Resource Management for Applications with Performance Constraints. 305-312 - Jürgen Teich, Michael Glaß, Sascha Roloff, Wolfgang Schröder-Preikschat, Gregor Snelting, Andreas Weichslgartner, Stefan Wildermann:
Language and Compilation of Parallel Programs for *-Predictable MPSoC Execution Using Invasive Computing. 313-320 - Peter P. Puschner, Bekim Cilku, Daniel Prokesch:
Constructing Time-Predictable MPSoCs: Avoid Conflicts in Temporal Control. 321-328
Special Session on Auto-Tuning for Multicore and GPU (ATMG) I
- Tomohiro Suzuki:
Faster Method for Tuning the Tile Size for Tile Matrix Decomposition. 329-336 - Seiji Nagashima, Takeshi Fukaya, Yusaku Yamamoto:
On Constructing Cost Models for Online Automatic Tuning Using ATMathCoreLib: Case Studies through the SVD Computation on a Multicore Processor. 345-352 - Shintaro Iwasaki, Kenjiro Taura:
Autotuning of a Cut-Off for Task Parallel Programs. 353-360
Special Session on Auto-Tuning for Multicore and GPU (ATMG) II
- Yue Hu, David M. Koppelman, Steven R. Brandt:
A Performance Model and Efficiency-Based Assignment of Buffering Strategies for Automatic GPU Stencil Code Generation. 361-368 - Ian Masliah, Marc Baboulin, Joël Falcou:
Meta-programming and Multi-stage Programming for GPGPUs. 369-376 - Daichi Mukunoki, Toshiyuki Imamura, Daisuke Takahashi:
Automatic Thread-Block Size Adjustment for Memory-Bound BLAS Kernels on GPUs. 377-384 - Hang Cui, Shoichi Hirasawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A Code Selection Mechanism Using Deep Learning. 385-392
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