13. VLSI Design 2000: Calcutta, India

Tutorials

Keynote Address

Thursday Plenary Talks

Session 1A: Low Power Design

Session 1B: Formal Verification:

Session 1C: Embedded Systems I

Session 2A: Digital Imaging I

Session 2B: Signal Integrity I

Session 2C: Testing I

Session 3A: High-level Synthesis

Session 3B: Layout & Floorplanning

Session 3C: Testing II

Banquet Address

Friday Plenary Talk

Session 4A: Digital Imaging II

Session 4B: Design

Session 4C: Signal Integrity II

Session 5A: Testing III

Session 5B: Verification

Session 5C: Embedded Systems II

Session 6A: Analog / Mixed-signal Circuits

Session 6B: Synthesis and Timing Analysis

Session 6C: Testing IV

VLSI Design 1999 Paper (late arrival)

maintained by Schloss Dagstuhl LZI at University of Trier