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ORCIDInternational Journal of Reconfigurable Computing, Volume 2017
Volume 2017, 2017
- Aous H. Kurdi
, Janos L. Grantner, Ikhlas Abdel-Qader:
Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection. 1325493:1-1325493:13 - Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Efficient Realization of BCD Multipliers Using FPGAs. 2410408:1-2410408:12 - Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera:
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. 6817674:1-6817674:11 - Gilberto Ochoa-Ruiz, Romain Bevan, Florent de Lamotte, Jean-Philippe Diguet, Cheng-Cong Bao:
Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform. 3298734:1-3298734:20 - Swapnil Mhaske, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic:
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. 3689308:1-3689308:23 - Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs:
Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language. 3925961:1-3925961:28 - Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid:
Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing. 7021056:1-7021056:9 - David Wilson, Aniruddha Shastri, Greg Stitt:
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. 5419767:1-5419767:17 - Satheesh Bojja Venkatakrishnan, Elias A. Alwan, John L. Volakis:
Challenges in Clock Synchronization for On-Site Coding Digital Beamformer. 7802735:1-7802735:8
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