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ORCIDIntegration, Volume 45
Volume 45, Number 1, January 2012
- Kishor Sarawadekar, Swapna Banerjee:
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. 1-8 - Emmanuel Casseau, Bertrand Le Gal:
Design of multi-mode application-specific cores based on high-level synthesis. 9-21 - Ali Peiravi
, Mohammad Asyaei:
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates. 22-32 - Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan:
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. 33-45 - Hao Qian, Yangdong Deng, Bo D. Wang, Shuai Mu:
Towards accelerating irregular EDA applications with GPUs. 46-60 - Stefan Scholze, Holger Eisenreich, Sebastian Höppner, Georg Ellguth, Stephan Henker, Mario Ander, Stefan Hänzsche, Johannes Partzsch, Christian Mayr, René Schüffny:
A 32 GBit/s communication SoC for a waferscale neuromorphic system. 61-75 - Chia-Chun Tsai, Chung-Chieh Kuo, Feng-Tzu Hsu, Trong-Yen Lee:
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree. 76-90 - Wenfa Zhan, Aiman El-Maleh:
A new scheme of test data compression based on equal-run-length coding (ERLC). 91-98 - Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer:
Fully hardware based WFQ architecture for high-speed QoS packet scheduling. 99-109
Volume 45, Number 2, March 2012
- Shahzad Asif, Mark Vesterbacka:
Performance analysis of radix-4 adders. 111-120 - Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham:
A new clock network synthesizer for modern VLSI designs. 121-131 - Jaeseong Kim, Shingo Yoshizawa, Yoshikazu Miyanaga:
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN. 132-140 - Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz:
An area efficient LDPC decoder using a reduced complexity min-sum algorithm. 141-148 - Selçuk Köse, Eby G. Friedman:
Efficient algorithms for fast IR drop analysis exploiting locality. 149-161 - Monica Figueiredo, Rui L. Aguiar:
A dynamic jitter model to evaluate uncertainty trends with technology scaling. 162-171 - Ruzica Jevtic, Carlos Carreras:
A complete dynamic power estimation model for data-paths in FPGA DSP designs. 172-185 - S. D. Pable, Mohd. Hasan:
Ultra-low-power signaling challenges for subthreshold global interconnects. 186-196 - Marinos Sampson, Marios Kalathas, Dimitrios Voudouris, George K. Papakonstantinou:
Exact ESOP expressions for incompletely specified functions. 197-204 - Sun-Mi Park:
Explicit formulae of polynomial basis squarer for pentanomials using weakly dual basis. 205-210 - S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay:
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing. 211-221 - Bernardo Palomo Vázquez, Fernando Muñoz, Ramón González Carvajal, José Ramón García Oya, Fernando J. Marquez:
An 8-bit 19 MS/s low-power 0.35 μm CMOS pipelined ADC for DVB-H. 222-227
Volume 45, Number 3, June 2012
- Wasim Hussain, Shah M. Jahinuzzaman:
A read-decoupled gated-ground SRAM architecture for low-power embedded memories. 229-236 - Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. 237-245 - Nivard Aymerich, Shrikanth Ganapathy, Antonio Rubio, Ramon Canal, Antonio González:
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells. 246-252 - Rahul Singh, Gi-Moon Hong, Mino Kim, Jihwan Park, Woo-Yeol Shin, Suhwan Kim:
Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers. 253-262 - Chenglong Xiao, Emmanuel Casseau:
Exact custom instruction enumeration for extensible processors. 263-270 - Nishit Ashok Kapadia, Sudeep Pasricha:
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands. 271-281 - Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
Synthesis of P-circuits for logic restructuring. 282-293 - Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José Monteiro:
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. 294-306 - Sujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay:
Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs. 307-315 - Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips. 316-330 - Ayantika Chatterjee, Indranil Sengupta:
Design of a high performance Binary Edwards Curve based processor secured against side channel analysis. 331-340 - Jin-Tai Yan, Zhi-Wei Chen:
New optimal layer assignment for bus-oriented escape routing. 341-347
Volume 45, Number 4, September 2012
- Jin-Tai Yan:
Resource-constrained link insertion for delay reduction. 349-356 - Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta:
SAT based timing analysis for fixed and rise/fall gate delay models. 357-364 - Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan:
An accurate sparse-matrix based framework for statistical static timing analysis. 365-375 - Hai Wang, Hao Yu, Sheldon X.-D. Tan:
Fast timing analysis of clock networks considering environmental uncertainty. 376-387
- Haridimos T. Vergos:
Area-time efficient end-around inverted carry adders. 388-394 - Fang Tang, Amine Bermak, Zhouye Gu:
Low power dynamic logic circuit design using a pseudo dynamic buffer. 395-404 - Po-Hsun Wu, Tsung-Yi Ho:
Bus-driven floorplanning with bus pin assignment and deviation minimization. 405-426 - Jasmina Vasiljevic, Andy Gean Ye:
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding. 427-438
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