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ORCIDACM Transactions on Architecture and Code Optimization, Volume 8
Volume 8, Number 1, April 2011
- Stijn Eyerman, Lieven Eeckhout:
Fine-grained DVFS using on-chip regulators. 1:1-1:24 - Chen-Yong Cher, Eren Kursun:
Exploring the effects of on-chip thermal variation on high-performance multicore architectures. 2:1-2:22 - Carole-Jean Wu, Margaret Martonosi:
Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches. 3:1-3:26 - Lucas Vespa, Ning Weng:
Deterministic finite automata characterization and optimization for scalable pattern matching. 4:1-4:31 - Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi:
Parallelization libraries: Characterizing and reducing overheads. 5:1-5:29
Volume 8, Number 2, July 2011
- Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. 6:1-6:29 - Jianjun Li, Chenggang Wu, Wei-Chung Hsu
:
Efficient and effective misaligned data access handling in a dynamic binary translation system. 7:1-7:29 - Guru Venkataramani, Christopher J. Hughes, Sanjeev Kumar, Milos Prvulovic:
DeFT: Design space exploration for on-the-fly detection of coherence misses. 8:1-8:27 - Jason Hiser, Daniel W. Williams, Wei Hu, Jack W. Davidson, Jason Mars, Bruce R. Childers:
Evaluating indirect branch handling mechanisms in software dynamic translation systems. 9:1-9:28
Volume 8, Number 3, October 2011
- Xi E. Chen, Tor M. Aamodt:
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. 10:1-10:28 - Marios Kleanthous, Yiannakis Sazeides:
CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches. 11:1-11:27 - Hans Vandierendonck, André Seznec:
Managing SMT resource usage through speculative instruction window weighting. 12:1-12:20 - Po-Han Wang, Chia-Lin Yang, Yen-Ming Chen, Yu-Jung Cheng:
Power gating strategies on GPUs. 13:1-13:25 - Min Feng, Chen Tian, Changhui Lin, Rajiv Gupta:
Dynamic access distance driven cache replacement. 14:1-14:30 - Ahmad Samih, Yan Solihin, Anil Krishna:
Evaluating placement policies for managing capacity sharing in CMP architectures with private caches. 15:1-15:23 - Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy. 16:1-16:27 - Hyunjin Lee, Sangyeun Cho, Bruce R. Childers:
DEFCAM: A design and evaluation framework for defect-tolerant cache memories. 17:1-17:29
Volume 8, Number 4, January 2012
- Per Stenström, Koen De Bosschere:
Introduction to the special issue on high-performance and embedded architectures and compilers. 18:1-18:2 - Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería:
ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. 19:1-19:20 - Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, Wayne P. Burleson:
An architecture-independent instruction shuffler to protect against side-channel attacks. 20:1-20:19 - John Demme, Simha Sethumadhavan:
Approximate graph clustering for program characterization. 21:1-21:21 - Mihai Pricopi, Tulika Mitra:
Bahurupi: A polymorphic heterogeneous multi-core architecture. 22:1-22:21 - Jeroen Van Cleemput, Bart Coppens, Bjorn De Sutter:
Compiler mitigations for time attacks on modern x86 processors. 23:1-23:20 - Jason McCandless, David Gregg:
Compiler techniques to improve dynamic branch prediction for indirect jump and call instructions. 24:1-24:20 - Antonio García-Guirado, Ricardo Fernández Pascual, Alberto Ros, José M. García:
DAPSCO: Distance-aware partially shared cache organization. 25:1-25:19 - Zhenjiang Wang, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Di Xu:
On-the-fly structure splitting for heap objects. 26:1-26:20 - Dibyendu Das, Benoît Dupont de Dinechin, Ramakrishna Upadrasta:
Efficient liveness computation using merge sets and DJ-graphs. 27:1-27:18 - George Patsilaras, Niket K. Choudhary, James Tuck:
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era. 28:1-28:21 - Roman Malits, Evgeny Bolotin, Avinoam Kolodny, Avi Mendelson:
Exploring the limits of GPGPU scheduling in control flow bound applications. 29:1-29:22 - Lois Orosa, Elisardo Antelo, Javier D. Bruguera:
FlexSig: Implementing flexible hardware signatures. 30:1-30:20 - J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. 31:1-31:20 - Yongjoo Kim, Jongeun Lee, Toan X. Mai, Yunheung Paek:
Improving performance of nested loops on reconfigurable array processors. 32:1-32:23 - Madhura Purnaprajna, Paolo Ienne:
Making wide-issue VLIW processors viable on FPGAs. 33:1-33:16 - Petar Radojkovic, Sylvain Girbal, Arnaud Grasset, Eduardo Quiñones, Sami Yehia, Francisco J. Cazorla:
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments. 34:1-34:25 - Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael B. Abu-Ghazaleh, Dmitry Ponomarev:
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks. 35:1-35:21 - Alejandro Rico, Felipe Cabarcas, Carlos Villavieja, Milan Pavlovic, Augusto Vega, Yoav Etsion, Alex Ramírez, Mateo Valero:
On the simulation of large-scale architectures using multiple application abstraction levels. 36:1-36:20 - Selma Saidi, Pranav Tendulkar, Thierry Lepley, Oded Maler:
Optimizing explicit data transfers for data parallel applications on the cell architecture. 37:1-37:20 - Min Feng, Changhui Lin, Rajiv Gupta:
PLDS: Partitioning linked data structures for parallelism. 38:1-38:21 - Benoît Pradelle, Alain Ketterlin, Philippe Clauss:
Polyhedral parallelization of binary code. 39:1-39:21 - Yaozu Dong, Yu Chen, Zhenhao Pan, Jinquan Dai, Yunhong Jiang:
ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication. 40:1-40:22 - Tom M. Bruintjes, Karel H. G. Walters, Sabih H. Gerez, Bert Molenkamp, Gerard J. M. Smit:
Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic. 41:1-41:22 - Mario Kicherer, Fabian Nowak, Rainer Buchty, Wolfgang Karl:
Seamlessly portable applications: Managing the diversity of modern heterogeneous systems. 42:1-42:20 - Nathanaël Prémillieu, André Seznec:
SYRANT: SYmmetric resource allocation on not-taken and taken paths. 43:1-43:20 - William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer:
The gradient-based cache partitioning algorithm. 44:1-44:21 - Javier Lira, Timothy M. Jones, Carlos Molina, Antonio González:
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches. 45:1-45:20 - Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan:
Thread Tranquilizer: Dynamically reducing performance variation. 46:1-46:21 - Dongsong Zhang, Deke Guo, Fang-Yuan Chen, Fei Wu, Tong Wu, Ting Cao, Shiyao Jin:
TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks. 47:1-47:20 - Michael J. Lyons, Mark Hempstead, Gu-Yeon Wei, David M. Brooks:
The accelerator store: A shared memory framework for accelerator-based systems. 48:1-48:22 - Daniel A. Orozco, Elkin Garcia, Rishi Khan, Kelly Livingston, Guang R. Gao:
Toward high-throughput algorithms on many-core architectures. 49:1-49:21 - Kevin Stock, Louis-Noël Pouchet, P. Sadayappan:
Using machine learning to improve automatic vectorization. 50:1-50:23 - Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman:
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. 51:1-51:19 - Frederick Ryckbosch, Stijn Polfliet, Lieven Eeckhout:
VSim: Simulating multi-server setups at near native hardware speed. 52:1-52:20 - Miao Zhou, Yu Du, Bruce R. Childers, Rami G. Melhem, Daniel Mossé:
Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems. 53:1-53:21 - Qingping Wang, Sameer Kulkarni, John Cavazos, Michael F. Spear:
A transactional memory with automatic performance tuning. 54:1-54:23 - Bartosz Bogdanski, Sven-Arne Reinemo, Frank Olaf Sem-Jacobsen, Ernst Gunnar Gran:
sFtree: A fully connected and deadlock-free switch-to-switch routing algorithm for fat-trees. 55:1-55:20
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