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ORCIDACM Transactions on Design Automation of Electronic Systems, Volume 20
Volume 20, Number 1, November 2014
- Naehyuck Chang, David Z. Pan, Yuan Xie:
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond. 1:1-1:2 - Wei Hu, Dejun Mu, Jason Oberg, Baolei Mao
, Mohit Tiwari, Timothy Sherwood, Ryan Kastner:
Gate-Level Information Flow Tracking for Security Lattices. 2:1-2:25 - Chun-Kai Wang, Yeh-Chi Chang, Hung-Ming Chen, Ching-Yu Chin:
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation. 3:1-3:23 - Lingyi Liu, Shobha Vasudevan:
Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL. 4:1-4:33 - Sharad Sinha, Thambipillai Srikanthan:
Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective. 5:1-5:18 - Graeme Gange, Harald Søndergaard, Peter J. Stuckey:
Synthesizing Optimal Switching Lattices. 6:1-6:14 - An-Che Cheng, Chia-Chih Jack Yen, Celina G. Val, Sam Bayless, Alan J. Hu, Iris Hui-Ru Jiang, Jing-Yang Jou:
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog. 7:1-7:23 - Xueliang Li, Guihai Yan, Yinhe Han, Xiaowei Li:
SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor. 8:1-8:16 - Wen-Li Shih, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee:
Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs. 9:1-9:34 - Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation. 10:1-10:25 - Seungcheol Baek, Hyung Gyu Lee, Chrysostomos Nicopoulos, Jongman Kim:
Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression. 11:1-11:31 - Hsien-Kai Kuo, Bo-Cheng Charles Lai, Jing-Yang Jou:
Reducing Contention in Shared Last-Level Cache for Throughput Processors. 12:1-12:28 - Roopak Sinha, Alain Girault, Gregor Goessler, Partha S. Roop:
A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design. 13:1-13:30 - Levent Aksoy, Paulo F. Flores, José Monteiro:
Multiplierless Design of Folded DSP Blocks. 14:1-14:24 - M. Mohamed Asan Basiri, Sk. Noor Mahammad:
An Efficient Hardware-Based Higher Radix Floating Point MAC Design. 15:1-15:25 - Cristiana Bolchini, Chiara Sandionigi:
Design of Hardened Embedded Systems on Multi-FPGA Platforms. 16:1-16:26
Volume 20, Number 2, February 2015
- Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng:
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method. 17:1-17:34 - Qi Guo, Tianshi Chen, Zhi-Hua Zhou, Olivier Temam, Ling Li, Depei Qian, Yunji Chen:
Robust Design Space Modeling. 18:1-18:22 - Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen:
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching. 19:1-19:23 - Nai-Wen Chang, Eddie Cheng, Sun-Yuan Hsieh:
Conditional Diagnosability of Cayley Graphs Generated by Transposition Trees under the PMC Model. 20:1-20:16 - Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto:
Data-Driven Optimization of Order Admission Policies in a Digital Print Factory. 21:1-21:25 - Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq Kuen Lee:
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems. 22:1-22:27 - Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi-Azad:
Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing. 23:1-23:24 - Xing Huang, Genggeng Liu, Wenzhong Guo, Yuzhen Niu, Guolong Chen:
Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design. 24:1-24:28 - Hung-Sheng Chang, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo, Hsiang-Pang Li:
Marching-Based Wear-Leveling for PCM-Based Storage Systems. 25:1-25:22 - Gang Chen, Kai Huang, Christian Buckl, Alois C. Knoll:
Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems. 26:1-26:27 - Franck Yonga, Michael Mefenza, Christophe Bobda:
ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks. 27:1-27:28 - Lok-Won Kim, Dong-U Lee, John D. Villasenor:
Automated Iterative Pipelining for ASIC Design. 28:1-28:24 - Irith Pomeranz:
A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences. 29:1-29:13 - Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation. 30:1-30:27 - Kamel Beznia, Ahcène Bounceur, Reinhardt Euler, Salvador Mir:
A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters. 31:1-31:22 - Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones:
A Fault-Aware Toolchain Approach for FPGA Fault Tolerance. 32:1-32:22 - Jiliang Zhang, Yaping Lin, Gang Qu:
Reconfigurable Binding against FPGA Replay Attacks. 33:1-33:20
Volume 20, Number 3, June 2015
- Meeta Srivastav, Mohammed Ehteshamuddin, Kyle Stegner, Leyla Nazhandali:
Design of Ultra-Low Power Scalable-Throughput Many-Core DSP Applications. 34:1-34:21 - Fahimeh Jafari, Zhonghai Lu, Axel Jantsch:
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels. 35:1-35:33 - Nicola Bombieri, Franco Fummi, Sara Vinco:
A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications. 36:1-36:26 - Stefan Holst, Michael E. Imhof, Hans-Joachim Wunderlich:
High-Throughput Logic Timing Simulation on GPGPUs. 37:1-37:22 - Tong Xu, Peng Li, Savithri Sundareswaran:
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating. 38:1-38:30 - Farshad Firouzi, Fangming Ye, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection. 39:1-39:23 - HeeJong Park, Avinash Malik, Zoran A. Salcic:
Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times. 40:1-40:25 - Qiuping Yi, Zijiang Yang, Jian Liu, Chen Zhao, Chao Wang:
Explaining Software Failures by Cascade Fault Localization. 41:1-41:28 - Jong Chul Lee, Roman L. Lysecky:
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems. 42:1-42:27 - Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Zili Shao:
Lazy-RTGC: A Real-Time Lazy Garbage Collection Mechanism with Jointly Optimizing Average and Worst Performance for NAND Flash Memory Storage Systems. 43:1-43:32 - Namita Sharma, Preeti Ranjan Panda, Francky Catthoor, Praveen Raghavan, Tom Vander Aa:
Array Interleaving - An Energy-Efficient Data Layout Transformation. 44:1-44:26 - Sudip Roy, Partha Pratim Chakrabarti, Srijan Kumar, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips. 45:1-45:34 - Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu:
Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation. 46:1-46:18
Volume 20, Number 4, September 2015
- Hai-Bao Chen, Ying-Chi Li, Sheldon X.-D. Tan, Xin Huang, Hai Wang, Ngai Wong:
H-Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs. 47:1-47:25 - Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
TCONMAP: Technology Mapping for Parameterised FPGA Configurations. 48:1-48:27 - Steffen Peter, Tony Givargis:
Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories. 49:1-49:27 - Ali Mirtar, Sujit Dey, Anand Raghunathan:
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding. 50:1-50:27 - Da-Wei Chang, Hsin-Hung Chen, Wei-Jian Su:
VSSD: Performance Isolation in a Solid-State Drive. 51:1-51:33 - Qing Duan, Abhishek Koneru, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto:
Accurate Analysis and Prediction of Enterprise Service-Level Performance. 52:1-52:23 - Ingoo Heo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent ByungHoon Kang, Yunheung Paek:
Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines. 53:1-53:32 - Lei Jiang, Bo Zhao, Jun Yang, Youtao Zhang:
Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology. 54:1-54:24 - Mohammad Hossein Samavatian, Mohammad Arjomand, Ramin Bashizade, Hamid Sarbazi-Azad:
Architecting the Last-Level Cache for GPUs using STT-RAM Technology. 55:1-55:24 - Leandro Soares Indrusiak, James Harbin, Osmar Marchi dos Santos:
Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration. 56:1-56:22 - Irith Pomeranz:
FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences. 57:1-57:19 - Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC. 58:1-58:24
- R. Iris Bahar, Alex K. Jones, Yuan Xie:
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. 59:1-59:2 - Bradley T. Kiddie, William H. Robinson, Daniel B. Limbrick:
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods. 60:1-60:22 - Leila Delshadtehrani, Hamed Farbeh, Seyed Ghassem Miremadi:
In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors. 61:1-61:28 - Nikolaos Papandreou, Thomas P. Parnell, Haralampos Pozidis, Thomas Mittelholzer, Evangelos Eleftheriou, Charles Camp, Thomas Griffin, Gary A. Tressler, Andrew Walls:
Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization. 62:1-62:24 - Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie:
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. 63:1-63:21 - Renyuan Zhang, Mineo Kaneko:
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism. 64:1-64:19 - Hyungjun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, Maria K. Michael:
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors. 65:1-65:26 - Andrew B. Kahng, Seokhyeong Kang, Jiajia Li, José Pineda de Gyvez:
An Improved Methodology for Resilient Design Implementation. 66:1-66:26
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