Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Daniel J. Friedman
@article{DBLP:journals/jssc/DicksonDCBKMCFB23,
author = {Timothy O. Dickson and
Zeynep Toprak Deniz and
Martin Cochet and
Troy J. Beukema and
Marcel A. Kossel and
Thomas Morf and
Young{-}Ho Choi and
Pier Andrea Francese and
Matthias Br{\"{a}}ndli and
Christian W. Baks and
Jonathan E. Proesel and
John F. Bulzacchelli and
Michael P. Beakes and
Byoung{-}Joo Yoo and
Hyoungbae Ahn and
Dong{-}Hyuk Lim and
Gunil Kang and
Sang{-}Hune Park and
Mounir Meghelli and
Hyo{-}Gyuem Rhew and
Daniel J. Friedman and
Michael Choi and
Mehmet Soyuer and
Jongshin Shin},
title = {A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET {CMOS}
for 200+ Gb/s Serial Links},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {4},
pages = {1074--1086},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3228632},
doi = {10.1109/JSSC.2022.3228632},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DicksonDCBKMCFB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/FrankCTRYGRRBRYDJLIUWBTSJGF23,
author = {David J. Frank and
Sudipto Chakraborty and
Kevin Tien and
Pat Rosno and
Mark Yeck and
Joseph A. Glick and
Raphael Robertazzi and
Ray Richetta and
John F. Bulzacchelli and
Daniel Ramirez and
Dereje Yilma and
Andrew Davies and
Rajiv V. Joshi and
Scott Lekuch and
Ken Inoue and
Devin Underwood and
Dorothy Wisnieff and
Chris Baks and
John Timmerwilke and
Peilin Song and
Blake R. Johnson and
Brian P. Gaucher and
Daniel J. Friedman},
title = {Low power cryogenic {RF} ASICs for quantum computing},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2023, San Antonio,
TX, USA, April 23-26, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CICC57935.2023.10121266},
doi = {10.1109/CICC57935.2023.10121266},
timestamp = {Sun, 21 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/FrankCTRYGRRBRYDJLIUWBTSJGF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/JoshiPZWCJWATTYYVF23,
author = {Rajiv V. Joshi and
Jean{-}Olivier Plouchart and
George Zettles and
Scott Willenborg and
Sudipto Chakraborty and
Blake R. Johnson and
Andrew Wack and
Brian Allison and
John Timmerwilke and
Kevin Tien and
Mark Yeck and
Dereje Yilma and
Alberto Valdes{-}Garcia and
Daniel J. Friedman},
title = {Cryogenic {CMOS:} design considerations for future quantum computing
systems},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2023, San Antonio,
TX, USA, April 23-26, 2023},
pages = {1--8},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CICC57935.2023.10121274},
doi = {10.1109/CICC57935.2023.10121274},
timestamp = {Sun, 21 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/JoshiPZWCJWATTYYVF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChakrabortyFTRY22,
author = {Sudipto Chakraborty and
David J. Frank and
Kevin Tien and
Pat Rosno and
Mark Yeck and
Joseph A. Glick and
Raphael Robertazzi and
Ray Richetta and
John F. Bulzacchelli and
Devin Underwood and
Daniel Ramirez and
Dereje Yilma and
Andrew Davies and
Rajiv V. Joshi and
Shawn D. Chambers and
Scott Lekuch and
Ken Inoue and
Dorothy Wisnieff and
Christian W. Baks and
Donald S. Bethune and
John Timmerwilke and
Thomas Fox and
Peilin Song and
Blake R. Johnson and
Brian P. Gaucher and
Daniel J. Friedman},
title = {A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller
in 14-nm FinFET Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {11},
pages = {3258--3273},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3201775},
doi = {10.1109/JSSC.2022.3201775},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChakrabortyFTRY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/TienILFCRFYGRRB22,
author = {Kevin Tien and
Ken Inoue and
Scott Lekuch and
David J. Frank and
Sudipto Chakraborty and
Pat Rosno and
Thomas Fox and
Mark Yeck and
Joseph A. Glick and
Raphael Robertazzi and
Ray Richetta and
John F. Bulzacchelli and
Daniel Ramirez and
Dereje Yilma and
Andrew Davies and
Rajiv V. Joshi and
Devin Underwood and
Dorothy Wisnieff and
Christian W. Baks and
Donald Bethune and
John Timmerwilke and
Blake R. Johnson and
Brian P. Gaucher and
Daniel J. Friedman},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {A Cryo-CMOS Transmon Qubit Controller and Verification with {FPGA}
Emulation},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {13--16},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774702},
doi = {10.23919/DATE54114.2022.9774702},
timestamp = {Wed, 25 May 2022 22:56:19 +0200},
biburl = {https://dblp.org/rec/conf/date/TienILFCRFYGRRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FrankCTRFYGRRBR22,
author = {David J. Frank and
Sudipto Chakraborty and
Kevin Tien and
Pat Rosno and
Thomas Fox and
Mark Yeck and
Joseph A. Glick and
Raphael Robertazzi and
Ray Richetta and
John F. Bulzacchelli and
Daniel Ramirez and
Dereje Yilma and
Andrew Davies and
Rajiv V. Joshi and
Shawn D. Chambers and
Scott Lekuch and
Ken Inoue and
Devin Underwood and
Dorothy Wisnieff and
Christian W. Baks and
Donald Bethune and
John Timmerwilke and
Blake R. Johnson and
Brian P. Gaucher and
Daniel J. Friedman},
title = {A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm
FinFET Technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
San Francisco, CA, USA, February 20-26, 2022},
pages = {360--362},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731538},
doi = {10.1109/ISSCC42614.2022.9731538},
timestamp = {Mon, 21 Mar 2022 13:32:47 +0100},
biburl = {https://dblp.org/rec/conf/isscc/FrankCTRFYGRRBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/DicksonDCKMCFBB22,
author = {Timothy O. Dickson and
Zeynep Toprak Deniz and
Martin Cochet and
Marcel A. Kossel and
Thomas Morf and
Young{-}Ho Choi and
Pier Andrea Francese and
Matthias Br{\"{a}}ndli and
Troy J. Beukema and
Christian W. Baks and
Jonathan E. Proesel and
John F. Bulzacchelli and
Michael P. Beakes and
Byoung{-}Joo Yoo and
Hyoungbae Ahn and
Dong{-}Hyuk Lim and
Gunil Kang and
Sang{-}Hune Park and
Mounir Meghelli and
Hyo{-}Gyuem Rhew and
Daniel J. Friedman and
Michael Choi and
Mehmet Soyuer and
Jongshin Shin},
title = {A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET {CMOS}
for 200+Gb/s Serial Links},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {28--29},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830421},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830421},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/DicksonDCKMCFBB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsit/YonarFBKMPRACDD22,
author = {Serdar S. Yonar and
Pier Andrea Francese and
Matthias Br{\"{a}}ndli and
Marcel A. Kossel and
Thomas Morf and
Jonathan E. Proesel and
Sergey V. Rylov and
Herschel A. Ainspan and
Martin Cochet and
Zeynep Toprak Deniz and
Timothy O. Dickson and
Troy J. Beukema and
Christian W. Baks and
Michael P. Beakes and
John F. Bulzacchelli and
Young{-}Ho Choi and
Byoung{-}Joo Yoo and
Hyoungbae Ahn and
Dong{-}Hyuk Lim and
Gunil Kang and
Sang{-}Hune Park and
Mounir Meghelli and
Hyo{-}Gyuem Rhew and
Daniel J. Friedman and
Michael Choi and
Mehmet Soyuer and
Jongshin Shin},
title = {An 8-bit 56GS/s 64x Time-Interleaved {ADC} with Bootstrapped Sampler
and Class-AB Buffer in 4nm {CMOS}},
booktitle = {{IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
pages = {168--169},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830308},
doi = {10.1109/VLSITECHNOLOGYANDCIR46769.2022.9830308},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/YonarFBKMPRACDD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FritschJCWSHTKR21,
author = {Alexander Fritsch and
Rajiv V. Joshi and
Sudipto Chakraborty and
Holger Wetter and
Uma Srinivasan and
Matthew Hyde and
Otto A. Torreiter and
Michael Kugel and
Dan Radko and
Hyong Kim and
Daniel J. Friedman},
title = {24.1 {A} 6.2 GHz Single Ended Current Sense Amplifier {(CSA)} Based
Compileable 8T {SRAM} in 7nm FinFET Technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {334--336},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365812},
doi = {10.1109/ISSCC42613.2021.9365812},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FritschJCWSHTKR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SadhuVPAGFYSGBL20,
author = {Bodhisatwa Sadhu and
Alberto Valdes{-}Garcia and
Jean{-}Olivier Plouchart and
Herschel A. Ainspan and
Arpit K. Gupta and
Mark A. Ferriss and
Mark Yeck and
Mihai Sanduleanu and
Xiaoxiong Gu and
Christian W. Baks and
Duixian Liu and
Daniel J. Friedman},
title = {A 250-mW 60-GHz {CMOS} Transceiver SoC Integrated With a Four-Element
AiP Providing Broad Angular Link Coverage},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {6},
pages = {1516--1529},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2943918},
doi = {10.1109/JSSC.2019.2943918},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SadhuVPAGFYSGBL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bcicts/Valdes-GarciaSG18,
author = {Alberto Valdes{-}Garcia and
Bodhisatwa Sadhu and
Xiaoxiong Gu and
Jean{-}Olivier Plouchart and
Mark Yeck and
Daniel J. Friedman},
title = {Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions},
booktitle = {2018 {IEEE} BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium (BCICTS), San Diego, CA, USA, October 15-17,
2018},
pages = {80--84},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/BCICTS.2018.8551062},
doi = {10.1109/BCICTS.2018.8551062},
timestamp = {Sun, 08 Aug 2021 01:40:59 +0200},
biburl = {https://dblp.org/rec/conf/bcicts/Valdes-GarciaSG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Friedman18,
author = {Daniel J. Friedman},
title = {{SC:} Hardware approaches to machine learning and inference},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {533--534},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310415},
doi = {10.1109/ISSCC.2018.8310415},
timestamp = {Sat, 20 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/Friedman18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SadhuTHSRRSHMBW17,
author = {Bodhisatwa Sadhu and
Yahya M. Tousi and
Joakim Hallin and
Stefan Sahl and
Scott K. Reynolds and
Orjan Renstrom and
Kristoffer Sjogren and
Olov Haapalahti and
Nadav Mazor and
Bo Bokinge and
Gustaf Weibull and
H{\aa}kan Bengtsson and
Anders Carlinger and
Eric Westesson and
Jan{-}Erik Thillberg and
Leonard Rexberg and
Mark Yeck and
Xiaoxiong Gu and
Mark A. Ferriss and
Duixian Liu and
Daniel J. Friedman and
Alberto Valdes{-}Garcia},
title = {A 28-GHz 32-Element {TRX} Phased-Array {IC} With Concurrent Dual-Polarized
Operation and Orthogonal Phase and Gain Control for 5G Communications},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {12},
pages = {3373--3391},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2017.2766211},
doi = {10.1109/JSSC.2017.2766211},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SadhuTHSRRSHMBW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SadhuTHSRRSHMBW17,
author = {Bodhisatwa Sadhu and
Yahya M. Tousi and
Joakim Hallin and
Stefan Sahl and
Scott K. Reynolds and
Orjan Renstrom and
Kristoffer Sjogren and
Olov Haapalahti and
Nadav Mazor and
Bo Bokinge and
Gustaf Weibull and
H{\aa}kan Bengtsson and
Anders Carlinger and
Eric Westesson and
Jan{-}Erik Thillberg and
Leonard Rexberg and
Mark Yeck and
Xiaoxiong Gu and
Daniel J. Friedman and
Alberto Valdes{-}Garcia},
title = {7.2 {A} 28GHz 32-element phased-array transceiver {IC} with concurrent
dual polarized beams and 1.4 degree beam-steering resolution for 5G
communication},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {128--129},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870294},
doi = {10.1109/ISSCC.2017.7870294},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SadhuTHSRRSHMBW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/Friedman17,
author = {Daniel J. Friedman},
title = {Ultra-low-power analog design},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {526--527},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870491},
doi = {10.1109/ISSCC.2017.7870491},
timestamp = {Sat, 20 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/Friedman17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DicksonLABADPBM16,
author = {Timothy O. Dickson and
Yong Liu and
Ankur Agrawal and
John F. Bulzacchelli and
Herschel A. Ainspan and
Zeynep Toprak Deniz and
Benjamin D. Parker and
Michael P. Beakes and
Mounir Meghelli and
Daniel J. Friedman},
title = {A 1.8 pJ/bit 16{\texttimes}16Gb/s Source-Synchronous Parallel Interface
in 32 nm {SOI} {CMOS} with Receiver Redundancy for Link Recalibration},
journal = {{IEEE} J. Solid State Circuits},
volume = {51},
number = {8},
pages = {1744--1755},
year = {2016},
url = {https://doi.org/10.1109/JSSC.2016.2550499},
doi = {10.1109/JSSC.2016.2550499},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DicksonLABADPBM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FerrissSRAF16,
author = {Mark A. Ferriss and
Bodhisatwa Sadhu and
Alexander V. Rylyakov and
Herschel A. Ainspan and
Daniel J. Friedman},
title = {10.8 {A} 12-to-26GHz fractional-N {PLL} with dual continuous tuning
LC-D/VCOs},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {196--198},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417974},
doi = {10.1109/ISSCC.2016.7417974},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FerrissSRAF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DicksonLRAKHBFA15,
author = {Timothy O. Dickson and
Yong Liu and
Sergey V. Rylov and
Ankur Agrawal and
Seongwon Kim and
Ping{-}Hsuan Hsieh and
John F. Bulzacchelli and
Mark A. Ferriss and
Herschel A. Ainspan and
Alexander V. Rylyakov and
Benjamin D. Parker and
Michael P. Beakes and
Christian W. Baks and
Lei Shan and
Young Hoon Kwark and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 1.4 pJ/bit, Power-Scalable 16{\texttimes}12 Gb/s Source-Synchronous
{I/O} With {DFE} Receiver in 32 nm {SOI} {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {8},
pages = {1917--1931},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2015.2412688},
doi = {10.1109/JSSC.2015.2412688},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/DicksonLRAKHBFA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/DicksonLABADPMF15,
author = {Timothy O. Dickson and
Yong Liu and
Ankur Agrawal and
John F. Bulzacchelli and
Herschel A. Ainspan and
Zeynep Toprak Deniz and
Benjamin D. Parker and
Mounir Meghelli and
Daniel J. Friedman},
title = {A 1.8-pJ/bit 16{\texttimes}16-Gb/s source synchronous parallel interface
in 32nm {SOI} {CMOS} with receiver redundancy for link recalibration},
booktitle = {2015 {IEEE} Custom Integrated Circuits Conference, {CICC} 2015, San
Jose, CA, USA, September 28-30, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CICC.2015.7338371},
doi = {10.1109/CICC.2015.7338371},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/DicksonLABADPMF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FerrissSRAF15,
author = {Mark A. Ferriss and
Bodhisatwa Sadhu and
Alexander V. Rylyakov and
Herschel A. Ainspan and
Daniel J. Friedman},
title = {10.9 {A} 13.1-to-28GHz fractional-N {PLL} in 32nm {SOI} {CMOS} with
a {\(\Delta\)}{\(\Sigma\)} noise-cancellation scheme},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062991},
doi = {10.1109/ISSCC.2015.7062991},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FerrissSRAF15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/PlouchartWLPSBSVF14,
author = {Jean{-}Olivier Plouchart and
Fa Wang and
Xin Li and
Benjamin D. Parker and
Mihai A. T. Sanduleanu and
Andreea Balteanu and
Bodhisatwa Sadhu and
Alberto Valdes{-}Garcia and
Daniel J. Friedman},
title = {Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave
Circuits},
journal = {{IEEE} Des. Test},
volume = {31},
number = {6},
pages = {8--18},
year = {2014},
url = {https://doi.org/10.1109/MDAT.2014.2343192},
doi = {10.1109/MDAT.2014.2343192},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/PlouchartWLPSBSVF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FerrissRTAF14,
author = {Mark A. Ferriss and
Alexander V. Rylyakov and
Jos{\'{e}} A. Tierno and
Herschel A. Ainspan and
Daniel J. Friedman},
title = {A 28 GHz Hybrid {PLL} in 32 nm {SOI} {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {4},
pages = {1027--1035},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2014.2299273},
doi = {10.1109/JSSC.2014.2299273},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/FerrissRTAF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SunWYLPNFPSPVSTF14,
author = {Shupeng Sun and
Fa Wang and
Soner Yaldiz and
Xin Li and
Lawrence T. Pileggi and
Arun Natarajan and
Mark A. Ferriss and
Jean{-}Olivier Plouchart and
Bodhisatwa Sadhu and
Benjamin D. Parker and
Alberto Valdes{-}Garcia and
Mihai A. T. Sanduleanu and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {Indirect Performance Sensing for On-Chip Self-Healing of Analog and
{RF} Circuits},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {61-I},
number = {8},
pages = {2243--2252},
year = {2014},
url = {https://doi.org/10.1109/TCSI.2014.2333311},
doi = {10.1109/TCSI.2014.2333311},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SunWYLPNFPSPVSTF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/DicksonLRAKHBFARPBSKTF14,
author = {Timothy O. Dickson and
Yong Liu and
Sergey V. Rylov and
Ankur Agrawal and
Seongwon Kim and
Ping{-}Hsuan Hsieh and
John F. Bulzacchelli and
Mark A. Ferriss and
Herschel A. Ainspan and
Alexander V. Rylyakov and
Benjamin D. Parker and
Christian W. Baks and
Lei Shan and
Young Hoon Kwark and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 1.4-pJ/b, power-scalable 16{\texttimes}12-Gb/s source-synchronous
{I/O} with {DFE} receiver in 32nm {SOI} {CMOS} technology},
booktitle = {Proceedings of the {IEEE} 2014 Custom Integrated Circuits Conference,
{CICC} 2014, San Jose, CA, USA, September 15-17, 2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/CICC.2014.6945983},
doi = {10.1109/CICC.2014.6945983},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/DicksonLRAKHBFARPBSKTF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sc/CassidyAASAMDTTAAEKAHBMBBMSCIMIMNVGNLAFJFRMM14,
author = {Andrew S. Cassidy and
Rodrigo Alvarez{-}Icaza and
Filipp Akopyan and
Jun Sawada and
John V. Arthur and
Paul Merolla and
Pallab Datta and
Marc Gonz{\'{a}}lez Tallada and
Brian Taba and
Alexander Andreopoulos and
Arnon Amir and
Steven K. Esser and
Jeff Kusnitz and
Rathinakumar Appuswamy and
Chuck Haymes and
Bernard Brezzo and
Roger Moussalli and
Ralph Bellofatto and
Christian W. Baks and
Michael Mastro and
Kai Schleupen and
Charles E. Cox and
Ken Inoue and
Steven E. Millman and
Nabil Imam and
Emmett McQuinn and
Yutaka Y. Nakamura and
Ivan Vo and
Chen Guok and
Don Nguyen and
Scott Lekuch and
Sameh W. Asaad and
Daniel J. Friedman and
Bryan L. Jackson and
Myron Flickner and
William P. Risk and
Rajit Manohar and
Dharmendra S. Modha},
editor = {Trish Damkroger and
Jack J. Dongarra},
title = {Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt
with {\textasciitilde}100{\texttimes} Speedup in Time-to-Solution
and {\textasciitilde}100, 000{\texttimes} Reduction in Energy-to-Solution},
booktitle = {International Conference for High Performance Computing, Networking,
Storage and Analysis, {SC} 2014, New Orleans, LA, USA, November 16-21,
2014},
pages = {27--38},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/SC.2014.8},
doi = {10.1109/SC.2014.8},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sc/CassidyAASAMDTTAAEKAHBMBBMSCIMIMNVGNLAFJFRMM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FerrissPNRPTBYVSF13,
author = {Mark A. Ferriss and
Jean{-}Olivier Plouchart and
Arun Natarajan and
Alexander V. Rylyakov and
Benjamin D. Parker and
Jos{\'{e}} A. Tierno and
Aydin Babakhani and
Soner Yaldiz and
Alberto Valdes{-}Garcia and
Bodhisatwa Sadhu and
Daniel J. Friedman},
title = {An Integral Path Self-Calibration Scheme for a Dual-Loop {PLL}},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {4},
pages = {996--1008},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2239114},
doi = {10.1109/JSSC.2013.2239114},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/FerrissPNRPTBYVSF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SadhuFNYPRVPBRLPHTF13,
author = {Bodhisatwa Sadhu and
Mark A. Ferriss and
Arun Natarajan and
Soner Yaldiz and
Jean{-}Olivier Plouchart and
Alexander V. Rylyakov and
Alberto Valdes{-}Garcia and
Benjamin D. Parker and
Aydin Babakhani and
Scott K. Reynolds and
Xin Li and
Lawrence T. Pileggi and
Ramesh Harjani and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A linearized, low-phase-noise VCO-based 25-GHz {PLL} with autonomic
biasing},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {5},
pages = {1138--1150},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2013.2252513},
doi = {10.1109/JSSC.2013.2252513},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SadhuFNYPRVPBRLPHTF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/PlouchartFNVSRPBBYPHRTF13,
author = {Jean{-}Olivier Plouchart and
Mark A. Ferriss and
A. S. Natarajan and
Alberto Valdes{-}Garcia and
Bodhisatwa Sadhu and
Alexander V. Rylyakov and
Benjamin D. Parker and
Michael P. Beakes and
Aydin Babakhani and
Soner Yaldiz and
Larry T. Pileggi and
Ramesh Harjani and
Scott K. Reynolds and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 23.5 GHz {PLL} With an Adaptively Biased {VCO} in 32 nm {SOI-CMOS}},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {60-I},
number = {8},
pages = {2009--2017},
year = {2013},
url = {https://doi.org/10.1109/TCSI.2013.2265961},
doi = {10.1109/TCSI.2013.2265961},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/PlouchartFNVSRPBBYPHRTF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SanduleanuVLPSSERF13,
author = {Mihai A. T. Sanduleanu and
Alberto Valdes{-}Garcia and
Y. Liu and
Benjamin D. Parker and
Shlomo Shlafman and
Benny Sheinman and
Danny Elad and
Scott K. Reynolds and
Daniel J. Friedman},
title = {A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability
in 32nm {CMOS} {SOI}},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658525},
doi = {10.1109/CICC.2013.6658525},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/SanduleanuVLPSSERF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SunWYLPNFPSPVSTF13,
author = {Shupeng Sun and
Fa Wang and
Soner Yaldiz and
Xin Li and
Lawrence T. Pileggi and
A. S. Natarajan and
Mark A. Ferriss and
Jean{-}Olivier Plouchart and
Bodhisatwa Sadhu and
Benjamin D. Parker and
Alberto Valdes{-}Garcia and
Mihai A. T. Sanduleanu and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {Indirect performance sensing for on-chip analog self-healing via Bayesian
model fusion},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658489},
doi = {10.1109/CICC.2013.6658489},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/SunWYLPNFPSPVSTF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/CowanMF13,
author = {Glenn E. R. Cowan and
Mounir Meghelli and
Daniel J. Friedman},
title = {A linearized voltage-controlled oscillator for dual-path phase-locked
loops},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {2678--2681},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572430},
doi = {10.1109/ISCAS.2013.6572430},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/CowanMF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuHKSMCTF13,
author = {Yong Liu and
Ping{-}Hsuan Hsieh and
Seongwon Kim and
Jae{-}sun Seo and
Robert K. Montoye and
Leland Chang and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power {I/O} for
on-chip signaling in 45nm {CMOS} {SOI}},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {400--401},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487787},
doi = {10.1109/ISSCC.2013.6487787},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LiuHKSMCTF13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BulzacchelliDRIBKBCCLTF12,
author = {John F. Bulzacchelli and
Zeynep Toprak Deniz and
Todd M. Rasmus and
Joseph A. Iadanza and
William L. Bucossi and
Seongwon Kim and
Rafael Blanco and
Carrie E. Cox and
Mohak Chhabra and
Christopher D. LeBlanc and
Christian L. Trudeau and
Daniel J. Friedman},
title = {Dual-Loop System of Distributed Microregulators With High {DC} Accuracy,
Load Response Time Below 500 ps, and 85-mV Dropout Voltage},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {863--874},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185354},
doi = {10.1109/JSSC.2012.2185354},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BulzacchelliDRIBKBCCLTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DicksonLRDTABAGTBPKF12,
author = {Timothy O. Dickson and
Yong Liu and
Sergey V. Rylov and
Bing Dang and
Cornelia K. Tsang and
Paul S. Andry and
John F. Bulzacchelli and
Herschel A. Ainspan and
Xiaoxiong Gu and
Lavanya Turlapati and
Michael P. Beakes and
Benjamin D. Parker and
John U. Knickerbocker and
Daniel J. Friedman},
title = {An 8x 10-Gb/s Source-Synchronous {I/O} System Based on High-Density
Silicon Carrier Interconnects},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {4},
pages = {884--896},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2185184},
doi = {10.1109/JSSC.2012.2185184},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DicksonLRDTABAGTBPKF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AgrawalBDLTF12,
author = {Ankur Agrawal and
John F. Bulzacchelli and
Timothy O. Dickson and
Yong Liu and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 19-Gb/s Serial Link Receiver With Both 4-Tap {FFE} and 5-Tap {DFE}
Functions in 45-nm {SOI} {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {12},
pages = {3220--3231},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2216412},
doi = {10.1109/JSSC.2012.2216412},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AgrawalBDLTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BulzacchelliMBSHHHRFGPMSKAKCRSGCBBKTF12,
author = {John F. Bulzacchelli and
Christian Menolfi and
Troy J. Beukema and
Daniel W. Storaska and
Juergen Hertle and
David Hanson and
Ping{-}Hsuan Hsieh and
Sergey V. Rylov and
Daniel Furrer and
Daniele Gardellini and
Andrea Prati and
Thomas Morf and
Vivek Sharma and
Ram Kelkar and
Herschel A. Ainspan and
W. R. Kelly and
L. R. Chieco and
Glenn Ritter and
J. A. Sorice and
Jon Garlett and
Robert Callan and
Matthias Braendli and
Peter Buchmann and
Marcel A. Kossel and
Thomas Toifl and
Daniel J. Friedman},
title = {A 28-Gb/s 4-Tap FFE/15-Tap {DFE} Serial Link Transceiver in 32-nm
{SOI} {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {12},
pages = {3232--3248},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2012.2216414},
doi = {10.1109/JSSC.2012.2216414},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BulzacchelliMBSHHHRFGPMSKAKCRSGCBBKTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/PlouchartFNVSRPBBYPHRTF12,
author = {Jean{-}Olivier Plouchart and
Mark A. Ferriss and
Arun Natarajan and
Alberto Valdes{-}Garcia and
Bodhisatwa Sadhu and
Alexander V. Rylyakov and
Benjamin D. Parker and
Michael P. Beakes and
Aydin Babakhani and
Soner Yaldiz and
Lawrence T. Pileggi and
Ramesh Harjani and
Scott K. Reynolds and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 23.5GHz {PLL} with an adaptively biased {VCO} in 32nm {SOI-CMOS}},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330593},
doi = {10.1109/CICC.2012.6330593},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/PlouchartFNVSRPBBYPHRTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/PlouchartSDBRPBTF12,
author = {Jean{-}Olivier Plouchart and
Mihai A. T. Sanduleanu and
Zeynep Toprak Deniz and
Troy J. Beukema and
Scott K. Reynolds and
Benjamin D. Parker and
Michael P. Beakes and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 3.2GS/s 4.55b {ENOB} two-step subranging {ADC} in 45nm {SOI} {CMOS}},
booktitle = {Proceedings of the {IEEE} 2012 Custom Integrated Circuits Conference,
{CICC} 2012, San Jose, CA, USA, September 9-12, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/CICC.2012.6330610},
doi = {10.1109/CICC.2012.6330610},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/PlouchartSDBRPBTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/AgrawalBDLTF12,
author = {Ankur Agrawal and
John F. Bulzacchelli and
Timothy O. Dickson and
Yong Liu and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {A 19Gb/s serial link receiver with both 4-tap {FFE} and 5-tap {DFE}
functions in 45nm {SOI} {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {134--136},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176951},
doi = {10.1109/ISSCC.2012.6176951},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/AgrawalBDLTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuLF12,
author = {Yong Liu and
Wing K. Luk and
Daniel J. Friedman},
title = {A compact low-power 3D {I/O} in 45nm {CMOS}},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {142--144},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6176900},
doi = {10.1109/ISSCC.2012.6176900},
timestamp = {Tue, 24 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiuLF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BulzacchelliBSHRFGPMHHMSKAKRGCTF12,
author = {John F. Bulzacchelli and
Troy J. Beukema and
Daniel W. Storaska and
Ping{-}Hsuan Hsieh and
Sergey V. Rylov and
Daniel Furrer and
Daniele Gardellini and
Andrea Prati and
Christian Menolfi and
David Hanson and
Juergen Hertle and
Thomas Morf and
Vivek Sharma and
Ram Kelkar and
Herschel A. Ainspan and
William Kelly and
Glenn Ritter and
Jon Garlett and
Robert Callan and
Thomas Toifl and
Daniel J. Friedman},
title = {A 28Gb/s 4-tap FFE/15-tap {DFE} serial link transceiver in 32nm {SOI}
{CMOS} technology},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {324--326},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177031},
doi = {10.1109/ISSCC.2012.6177031},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/BulzacchelliBSHRFGPMHHMSKAKRGCTF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FerrissPNRPBYSV12,
author = {Mark A. Ferriss and
Jean{-}Olivier Plouchart and
Arun Natarajan and
Alexander V. Rylyakov and
Benjamin D. Parker and
Aydin Babakhani and
Soner Yaldiz and
Bodhisatwa Sadhu and
Alberto Valdes{-}Garcia and
Jos{\'{e}} A. Tierno and
Daniel J. Friedman},
title = {An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop
{PLL} in 32nm {SOI} {CMOS}},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {176--177},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243847},
doi = {10.1109/VLSIC.2012.6243847},
timestamp = {Fri, 02 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/FerrissPNRPBYSV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SeoBLPEMRTCMF11,
author = {Jae{-}sun Seo and
Bernard Brezzo and
Yong Liu and
Benjamin D. Parker and
Steven K. Esser and
Robert K. Montoye and
Bipin Rajendran and
Jos{\'{e}} A. Tierno and
Leland Chang and
Dharmendra S. Modha and
Daniel J. Friedman},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {A 45nm {CMOS} neuromorphic chip with a scalable architecture for learning
in networks of spiking neurons},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055293},
doi = {10.1109/CICC.2011.6055293},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/SeoBLPEMRTCMF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jamia/FriedmanP10,
author = {Daniel J. Friedman and
R. Gibson Parrish II},
title = {The population health record: concepts, definition, design, and implementation},
journal = {J. Am. Medical Informatics Assoc.},
volume = {17},
number = {4},
pages = {359--366},
year = {2010},
url = {https://doi.org/10.1136/jamia.2009.001578},
doi = {10.1136/JAMIA.2009.001578},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jamia/FriedmanP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DicksonBF09,
author = {Timothy O. Dickson and
John F. Bulzacchelli and
Daniel J. Friedman},
title = {A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer
With Current-Integrating Summers in 45-nm {SOI} {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {4},
pages = {1298--1305},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2014733},
doi = {10.1109/JSSC.2009.2014733},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DicksonBF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimLDBF09,
author = {Byungsub Kim and
Yong Liu and
Timothy O. Dickson and
John F. Bulzacchelli and
Daniel J. Friedman},
title = {A 10-Gb/s Compact Low-Power Serial {I/O} With {DFE-IIR} Equalization
in 65-nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {12},
pages = {3526--3538},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2031015},
doi = {10.1109/JSSC.2009.2031015},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimLDBF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RylyakovTAPBDF09,
author = {Alexander V. Rylyakov and
Jos{\'{e}} A. Tierno and
Herschel A. Ainspan and
Jean{-}Olivier Plouchart and
John F. Bulzacchelli and
Zeynep Toprak Deniz and
Daniel J. Friedman},
title = {Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter
for high-speed serial communication applications},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {94--95},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977324},
doi = {10.1109/ISSCC.2009.4977324},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/RylyakovTAPBDF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimDFCKRF09,
author = {Kyu{-}Hyoun Kim and
Daniel M. Dreps and
Frank D. Ferraiolo and
Paul W. Coteus and
Seongwon Kim and
Sergey V. Rylov and
Daniel J. Friedman},
title = {A 5.4mW 0.0035mm\({}^{\mbox{2}}\) 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL
all-digital phase generator/rotator in 45nm {SOI} {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {98--99},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977326},
doi = {10.1109/ISSCC.2009.4977326},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimDFCKRF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuKDBF09,
author = {Yong Liu and
Byungsub Kim and
Timothy O. Dickson and
John F. Bulzacchelli and
Daniel J. Friedman},
title = {A 10Gb/s compact low-power serial {I/O} with {DFE-IIR} equalization
in 65nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {182--183},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977368},
doi = {10.1109/ISSCC.2009.4977368},
timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/LiuKDBF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/BulzacchelliDDAPBRF09,
author = {John F. Bulzacchelli and
Timothy O. Dickson and
Zeynep Toprak Deniz and
Herschel A. Ainspan and
Benjamin D. Parker and
Michael P. Beakes and
Sergey V. Rylov and
Daniel J. Friedman},
title = {A 78mW 11.1Gb/s 5-tap {DFE} receiver with digitally calibrated current-integrating
summers in 65nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {368--369},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977461},
doi = {10.1109/ISSCC.2009.4977461},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/BulzacchelliDDAPBRF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TiernoRF08,
author = {Jos{\'{e}} A. Tierno and
Alexander V. Rylyakov and
Daniel J. Friedman},
title = {A Wide Power Supply Range, Wide Tuning Range, All Static {CMOS} All
Digital {PLL} in 65 nm {SOI}},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {1},
pages = {42--51},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2007.910966},
doi = {10.1109/JSSC.2007.910966},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TiernoRF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/RylyakovTESF08,
author = {Alexander V. Rylyakov and
Jos{\'{e}} A. Tierno and
George English and
Michael A. Sperling and
Daniel J. Friedman},
title = {A wide tuning range {(1} GHz-to-15 GHz) fractional-N all-digital {PLL}
in 45nm {SOI}},
booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
{CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
21-24, 2008},
pages = {431--434},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/CICC.2008.4672113},
doi = {10.1109/CICC.2008.4672113},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/RylyakovTESF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KimCDKRF08,
author = {Kyu{-}Hyoun Kim and
Paul W. Coteus and
Daniel M. Dreps and
Seongwon Kim and
Sergey V. Rylov and
Daniel J. Friedman},
title = {A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {458--459},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523255},
doi = {10.1109/ISSCC.2008.4523255},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KimCDKRF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RylyakovTTPAF08,
author = {Alexander V. Rylyakov and
Jos{\'{e}} A. Tierno and
Didem Zeliha Turker and
Jean{-}Olivier Plouchart and
Herschel A. Ainspan and
Daniel J. Friedman},
title = {A Modular All-Digital {PLL} Architecture Enabling Both 1-to-2GHz and
24-to-32GHz Operation in 65nm {CMOS}},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {516--517},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523284},
doi = {10.1109/ISSCC.2008.4523284},
timestamp = {Wed, 10 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/RylyakovTTPAF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/Emami-Neyestanak07,
author = {Azita Emami{-}Neyestanak and
Aida Varzaghani and
John F. Bulzacchelli and
Alexander V. Rylyakov and
Chih{-}Kong Ken Yang and
Daniel J. Friedman},
title = {A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation {DFE}},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {4},
pages = {889--896},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2007.892156},
doi = {10.1109/JSSC.2007.892156},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/Emami-Neyestanak07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SoltanianARFK07,
author = {Babak Soltanian and
Herschel A. Ainspan and
Woogeun Rhee and
Daniel J. Friedman and
Peter R. Kinget},
title = {An Ultra-Compact Differentially Tuned 6-GHz {CMOS} {LC-VCO} With Dynamic
Common-Mode Feedback},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {8},
pages = {1635--1641},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2007.903068},
doi = {10.1109/JSSC.2007.903068},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SoltanianARFK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/RylyakovTEFM07,
author = {Alexander V. Rylyakov and
Jos{\'{e}} A. Tierno and
George English and
Daniel J. Friedman and
M. Megheli},
title = {A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range {(500}
MHz-to-8 GHz) All-Static {CMOS} {AD} {PLL} in 65nm {SOI}},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {172--173},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373349},
doi = {10.1109/ISSCC.2007.373349},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/RylyakovTEFM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/LiuRFH07,
author = {Yong Liu and
Woogeun Rhee and
Daniel J. Friedman and
Donhee Ham},
title = {All-Digital Dynamic Self-Detection and Self-Compensation of Static
Phase Offsets in Charge-Pump PLLs},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {176--595},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373351},
doi = {10.1109/ISSCC.2007.373351},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/LiuRFH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ParkBBF07,
author = {Matt Park and
John F. Bulzacchelli and
Michael P. Beakes and
Daniel J. Friedman},
title = {A 7Gb/s 9.3mW 2-Tap Current-Integrating {DFE} Receiver},
booktitle = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2007, Digest of Technical Papers, San Francisco, CA, USA, February
11-15, 2007},
pages = {230--599},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISSCC.2007.373378},
doi = {10.1109/ISSCC.2007.373378},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ParkBBF07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BuckwalterMFH06,
author = {James F. Buckwalter and
Mounir Meghelli and
Daniel J. Friedman and
Ali Hajimiri},
title = {Phase and amplitude pre-emphasis techniques for low-power serial links},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {6},
pages = {1391--1399},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2006.874270},
doi = {10.1109/JSSC.2006.874270},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/BuckwalterMFH06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BulzacchelliMRR06,
author = {John F. Bulzacchelli and
Mounir Meghelli and
Sergey V. Rylov and
Woogeun Rhee and
Alexander V. Rylyakov and
Herschel A. Ainspan and
Benjamin D. Parker and
Michael P. Beakes and
Aichin Chung and
Troy J. Beukema and
Petar K. Pepeljugoski and
Lei Shan and
Young Hoon Kwark and
Sudhir M. Gowda and
Daniel J. Friedman},
title = {A 10-Gb/s 5-Tap DFE/4-Tap {FFE} Transceiver in 90-nm {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {12},
pages = {2885--2900},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2006.884342},
doi = {10.1109/JSSC.2006.884342},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BulzacchelliMRR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/SoltanianARFK06,
author = {Baharak Soltanian and
Herschel A. Ainspan and
Woogeun Rhee and
Daniel J. Friedman and
Peter R. Kinget},
title = {An Ultra Compact Differentially Tuned 6 GHz {CMOS} {LC} {VCO} with
Dynamic Common-Mode Feedback},
booktitle = {Proceedings of the {IEEE} 2006 Custom Integrated Circuits Conference,
{CICC} 2006, DoubleTree Hotel, San Jose, California, USA, September
10-13, 2006},
pages = {671--674},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/CICC.2006.320877},
doi = {10.1109/CICC.2006.320877},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/SoltanianARFK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MeghelliRBRRAPB06,
author = {Mounir Meghelli and
Sergey V. Rylov and
John F. Bulzacchelli and
Woogeun Rhee and
Alexander V. Rylyakov and
Herschel A. Ainspan and
Benjamin D. Parker and
Michael P. Beakes and
Aichin Chung and
Troy J. Beukema and
Petar K. Pepeljugoski and
L. Shan and
Young Hoon Kwark and
Sudhir M. Gowda and
Daniel J. Friedman},
title = {A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm {CMOS}},
booktitle = {2006 {IEEE} International Solid State Circuits Conference, {ISSCC}
2006, Digest of Technical Papers, an Francisco, CA, USA, February
6-9, 2006},
pages = {213--222},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISSCC.2006.1696051},
doi = {10.1109/ISSCC.2006.1696051},
timestamp = {Fri, 15 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MeghelliRBRRAPB06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/RheePF04,
author = {Woogeun Rhee and
Benjamin D. Parker and
Daniel J. Friedman},
title = {A semi-digital delay-locked loop using an analog-based finite state
machine},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {51-II},
number = {11},
pages = {635--639},
year = {2004},
url = {https://doi.org/10.1109/TCSII.2004.836035},
doi = {10.1109/TCSII.2004.836035},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/RheePF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/FriedmanMPYARKRSZSS03,
author = {Daniel J. Friedman and
Mounir Meghelli and
Benjamin D. Parker and
Jungwook Yang and
Herschel A. Ainspan and
Alexander V. Rylyakov and
Young Hoon Kwark and
Mark B. Ritter and
Lei Shan and
Steven J. Zier and
Michael Sorna and
Mehmet Soyuer},
title = {SiGe BiCMOS integrated circuits for high-speed serial communication
links},
journal = {{IBM} J. Res. Dev.},
volume = {47},
number = {2-3},
pages = {259--282},
year = {2003},
url = {https://doi.org/10.1147/rd.472.0259},
doi = {10.1147/RD.472.0259},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/FriedmanMPYARKRSZSS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MeghelliRZSF03,
author = {Mounir Meghelli and
Alexander V. Rylyakov and
Steven Zier and
Michael Sorna and
Daniel J. Friedman},
title = {A 0.18-{\(\mu\)}m SiGe BiCMOS receiver and transmitter chipset for
{SONET} {OC-768} transmission systems},
journal = {{IEEE} J. Solid State Circuits},
volume = {38},
number = {12},
pages = {2147--2154},
year = {2003},
url = {https://doi.org/10.1109/JSSC.2003.818571},
doi = {10.1109/JSSC.2003.818571},
timestamp = {Wed, 20 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MeghelliRZSF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/RheeARRBFGS03,
author = {Woogeun Rhee and
Herschel A. Ainspan and
Sergey V. Rylov and
Alexander V. Rylyakov and
Michael P. Beakes and
Daniel J. Friedman and
Sudhir M. Gowda and
Mehmet Soyuer},
title = {A 10-Gb/s {CMOS} clock and data recovery circuit using a secondary
delay-locked loop},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {81--84},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249364},
doi = {10.1109/CICC.2003.1249364},
timestamp = {Mon, 15 Nov 2021 17:53:34 +0100},
biburl = {https://dblp.org/rec/conf/cicc/RheeARRBFGS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KimKMRKF03,
author = {Seongwon Kim and
Mohit Kapur and
Mounir Meghelli and
Alexander V. Rylyakov and
Young Hoon Kwark and
Daniel J. Friedman},
title = {45-Gb/s SiGe BiCMOS {PRBS} generator and {PRBS} checker [pseudorandom
bit sequence]},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {313--316},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249410},
doi = {10.1109/CICC.2003.1249410},
timestamp = {Mon, 15 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/KimKMRKF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/ClarkF91,
author = {James J. Clark and
Daniel J. Friedman},
title = {{VLSI} sensori-motor systems},
booktitle = {Proceedings of the 1991 {IEEE} International Conference on Robotics
and Automation, Sacramento, CA, USA, 9-11 April 1991},
pages = {1342--1347},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ROBOT.1991.131799},
doi = {10.1109/ROBOT.1991.131799},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icra/ClarkF91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 05:45 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
