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BibTeX records: Kyung-Soo Ha
@article{DBLP:journals/jssc/HaLPKOSBPLLLMHP20, author = {Kyung{-}Soo Ha and Seungseob Lee and Youn{-}Sik Park and Hyuck{-}Joon Kwon and Tae{-}Young Oh and Young{-}Soo Sohn and Seung{-}Jun Bae and Kwang{-}Il Park and Jung{-}Bae Lee and Chang{-}Kyo Lee and Dongkeon Lee and Daesik Moon and Hyong{-}Ryol Hwang and Dukha Park and Young{-}Hwa Kim and Young Hoon Son and Byongwook Na}, title = {A 7.5 Gb/s/pin 8-Gb {LPDDR5} {SDRAM} With Various High-Speed and Low-Power Techniques}, journal = {{IEEE} J. Solid State Circuits}, volume = {55}, number = {1}, pages = {157--166}, year = {2020}, url = {https://doi.org/10.1109/JSSC.2019.2938396}, doi = {10.1109/JSSC.2019.2938396}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/HaLPKOSBPLLLMHP20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/HaLLMJHCPSPKLPC19, author = {Kyung{-}Soo Ha and Chang{-}Kyo Lee and Dongkeon Lee and Daesik Moon and Jin{-}Hun Jang and Hyong{-}Ryol Hwang and Hyung{-}Joon Chi and Junghwan Park and Seungjun Shin and Dukha Park and Sang{-}Yun Kim and Sukhyun Lim and Kiwon Park and YeonKyu Choi and Young{-}Hwa Kim and Younghoon Son and Hyunyoon Cho and Byongwook Na and Hyo{-}Joo Ahn and Seungseob Lee and Seouk{-}Kyu Choi and Youn{-}Sik Park and Seok{-}Hun Hyun and Soobong Chang and Hyuck{-}Joon Kwon and Jung{-}Hwan Choi and Tae{-}Young Oh and Young{-}Soo Sohn and Kwang{-}Il Park and Seong{-}Jin Jang}, title = {A 7.5Gb/s/pin {LPDDR5} {SDRAM} With {WCK} Clocking and Non-Target {ODT} for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power}, booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019, San Francisco, CA, USA, February 17-21, 2019}, pages = {378--380}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.1109/ISSCC.2019.8662509}, doi = {10.1109/ISSCC.2019.8662509}, timestamp = {Tue, 05 Mar 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isscc/HaLLMJHCPSPKLPC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/LeeLKHBCMLPLCCH18, author = {Chang{-}Kyo Lee and Junha Lee and Kiho Kim and Jin{-}Seok Heo and Jin{-}Hyeok Baek and Gil{-}Hoon Cha and Daesik Moon and Dong{-}Hun Lee and Jong{-}Wook Park and Seunseob Lee and Si{-}Hyeong Cho and Young{-}Ryeol Choi and Kyung{-}Soo Ha and Eunsung Seo and Youn{-}Sik Park and Seung{-}Jun Bae and Indal Song and Seok{-}Hun Hyun and Hyuck{-}Joon Kwon and Young{-}Soo Sohn and Jung{-}Hwan Choi and Kwang{-}Il Park and Seong{-}Jin Jang}, title = {Dual-Loop Two-Step {ZQ} Calibration for Dynamic Voltage-Frequency Scaling in {LPDDR4} {SDRAM}}, journal = {{IEEE} J. Solid State Circuits}, volume = {53}, number = {10}, pages = {2906--2916}, year = {2018}, url = {https://doi.org/10.1109/JSSC.2018.2850937}, doi = {10.1109/JSSC.2018.2850937}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/LeeLKHBCMLPLCCH18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/ChunCHKKYKLKYSC18, author = {Ki Chul Chun and Yong{-}Gyu Chu and Jin{-}Seok Heo and Tae{-}Sung Kim and Soohwan Kim and Hui{-}Kap Yang and Mi{-}Jo Kim and Chang{-}Kyo Lee and Ju{-}Hwan Kim and Hyunchul Yoon and Chang{-}Ho Shin and Sang{-}uhn Cha and Hyung{-}Jin Kim and Young{-}Sik Kim and Kyungryun Kim and Young{-}Ju Kim and Won{-}Jun Choi and Dae{-}Sik Yim and Inkyu Moon and Young{-}Ju Kim and Junha Lee and Young Choi and Yongmin Kwon and Sung{-}Won Choi and Jung{-}Wook Kim and Yoon{-}Suk Park and Woongdae Kang and Jinil Chung and Seunghyun Kim and Yesin Ryu and Seong{-}Jin Cho and Hoon Shin and Hangyun Jung and Sanghyuk Kwon and Kyuchang Kang and Jongmyung Lee and Yujung Song and Youngjae Kim and Eun{-}Ah Kim and Kyung{-}Soo Ha and Kyoung{-}Ho Kim and Seok{-}Hun Hyun and Seung{-}Bum Ko and Jung{-}Hwan Choi and Young{-}Soo Sohn and Kwang{-}Il Park and Seong{-}Jin Jang}, title = {A 16Gb {LPDDR4X} {SDRAM} with an NBTI-tolerant circuit solution, an {SWD} {PMOS} {GIDL} reduction technique, an adaptive gear-down scheme and a metastable-free {DQS} aligner in a 10nm class {DRAM} process}, booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2018, San Francisco, CA, USA, February 11-15, 2018}, pages = {206--208}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/ISSCC.2018.8310256}, doi = {10.1109/ISSCC.2018.8310256}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/ChunCHKKYKLKYSC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/JooBSKHA0KKKCSK16, author = {Hye{-}Yoon Joo and Seung{-}Jun Bae and Young{-}Soo Sohn and Young{-}Sik Kim and Kyung{-}Soo Ha and Min{-}Su Ahn and Young{-}Ju Kim and Yong{-}Jun Kim and Ju{-}Hwan Kim and Won{-}Jun Choi and Chang{-}Ho Shin and Soo Hwan Kim and Byeong{-}Cheol Kim and Seung{-}Bum Ko and Kwang{-}Il Park and Seong{-}Jin Jang and Gyo{-}Young Jin}, title = {18.1 {A} 20nm 9Gb/s/pin 8Gb {GDDR5} {DRAM} with an {NBTI} monitor, jitter reduction techniques and improved power distribution}, booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC} 2016, San Francisco, CA, USA, January 31 - February 4, 2016}, pages = {314--315}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ISSCC.2016.7418033}, doi = {10.1109/ISSCC.2016.7418033}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/JooBSKHA0KKKCSK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/OhCPLODKLKLLHCCBJPPJC15, author = {Tae{-}Young Oh and Hoeju Chung and Jun{-}Young Park and Ki{-}Won Lee and Seung{-}Hoon Oh and Su{-}Yeon Doo and Hyoung{-}Joo Kim and ChangYong Lee and Hye{-}Ran Kim and Jong{-}Ho Lee and Jin{-}Il Lee and Kyung{-}Soo Ha and Young{-}Ryeol Choi and Young{-}Chul Cho and Yong{-}Cheol Bae and Taeseong Jang and Chulsung Park and Kwang{-}Il Park and Seong{-}Jin Jang and Joo{-}Sun Choi}, title = {A 3.2 Gbps/pin 8 Gbit 1.0 {V} {LPDDR4} {SDRAM} With Integrated {ECC} Engine for Sub-1 {V} {DRAM} Core Operation}, journal = {{IEEE} J. Solid State Circuits}, volume = {50}, number = {1}, pages = {178--190}, year = {2015}, url = {https://doi.org/10.1109/JSSC.2014.2353799}, doi = {10.1109/JSSC.2014.2353799}, timestamp = {Wed, 05 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/jssc/OhCPLODKLKLLHCCBJPPJC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcas/KimCHBK15, author = {Young{-}Ju Kim and Sang{-}Hye Chung and Kyung{-}Soo Ha and Seung{-}Jun Bae and Lee{-}Sup Kim}, title = {A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator}, journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.}, volume = {62-I}, number = {10}, pages = {2495--2503}, year = {2015}, url = {https://doi.org/10.1109/TCSI.2015.2459557}, doi = {10.1109/TCSI.2015.2459557}, timestamp = {Fri, 22 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcas/KimCHBK15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcas/ChungKHBLK14, author = {Sang{-}Hye Chung and Young{-}Ju Kim and Kyung{-}Soo Ha and Seung{-}Jun Bae and Jung{-}Bae Lee and Lee{-}Sup Kim}, title = {A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth}, journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs}, volume = {61-II}, number = {3}, pages = {153--157}, year = {2014}, url = {https://doi.org/10.1109/TCSII.2013.2296134}, doi = {10.1109/TCSII.2013.2296134}, timestamp = {Wed, 27 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcas/ChungKHBLK14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/OhCCRLLLKJHKMBP14, author = {Tae{-}Young Oh and Hoeju Chung and Young{-}Chul Cho and Jang{-}Woo Ryu and Kiwon Lee and Changyoung Lee and Jin{-}Il Lee and Hyoung{-}Joo Kim and Min{-}Soo Jang and Gong{-}Heum Han and Kihan Kim and Daesik Moon and Seung{-}Jun Bae and Joon{-}Young Park and Kyung{-}Soo Ha and Jaewoong Lee and Su{-}Yeon Doo and Jung{-}Bum Shin and Chang{-}Ho Shin and Kiseok Oh and Doo{-}Hee Hwang and Taeseong Jang and Chulsung Park and Kwang{-}Il Park and Jung{-}Bae Lee and Joo{-}Sun Choi}, title = {25.1 {A} 3.2Gb/s/pin 8Gb 1.0V {LPDDR4} {SDRAM} with integrated {ECC} engine for sub-1V {DRAM} core operation}, booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference, {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014}, pages = {430--431}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/ISSCC.2014.6757500}, doi = {10.1109/ISSCC.2014.6757500}, timestamp = {Wed, 05 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isscc/OhCCRLLLKJHKMBP14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/SeolKCHBLCK13, author = {Ji{-}Hwan Seol and Young{-}Ju Kim and Sang{-}Hye Chung and Kyung{-}Soo Ha and Seung{-}Jun Bae and Jung{-}Bae Lee and Joo{-}Sun Choi and Lee{-}Sup Kim}, title = {An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an {ILO} with dual feedback loop and quadrature injection scheme}, booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February 17-21, 2013}, pages = {410--411}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/ISSCC.2013.6487792}, doi = {10.1109/ISSCC.2013.6487792}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/SeolKCHBLCK13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/HaKBPCJK09, author = {Kyung{-}Soo Ha and Lee{-}Sup Kim and Seung{-}Jun Bae and Kwang{-}Il Park and Joo{-}Sun Choi and Young{-}Hyun Jun and Kinam Kim}, title = {A 0.13-{\(\mathrm{\mu}\)}m {CMOS} 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to {SSN}}, journal = {{IEEE} J. Solid State Circuits}, volume = {44}, number = {11}, pages = {3146--3162}, year = {2009}, url = {https://doi.org/10.1109/JSSC.2009.2031527}, doi = {10.1109/JSSC.2009.2031527}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/HaKBPCJK09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/HaKBPCJK09, author = {Kyung{-}Soo Ha and Lee{-}Sup Kim and Seung{-}Jun Bae and Kwang{-}Il Park and Joo{-}Sun Choi and Young{-}Hyun Jun and Kinam Kim}, title = {A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for {DRAM} interfaces}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009}, pages = {138--139}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ISSCC.2009.4977346}, doi = {10.1109/ISSCC.2009.4977346}, timestamp = {Wed, 16 Oct 2019 14:14:55 +0200}, biburl = {https://dblp.org/rec/conf/isscc/HaKBPCJK09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/HaK06, author = {Kyung{-}Soo Ha and Lee{-}Sup Kim}, title = {Charge-pump reducing current mismatch in DLLs and PLLs}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24 May 2006, Island of Kos, Greece}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ISCAS.2006.1693061}, doi = {10.1109/ISCAS.2006.1693061}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/HaK06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/HongHK06, author = {Ju{-}Pyo Hong and Kyung{-}Soo Ha and Lee{-}Sup Kim}, title = {A 0.18{\(\mathrm{\mu}\)}m {CMOS} 10Gb/s 1: 4 {DEMUX} using replica-bias circuits for optical receiver}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24 May 2006, Island of Kos, Greece}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/ISCAS.2006.1693931}, doi = {10.1109/ISCAS.2006.1693931}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/iscas/HongHK06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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