BibTeX records: Chieh-Pu Lo

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@inproceedings{DBLP:conf/isscc/WangYLK24,
  author       = {Yipeng Wang and
                  Mengtian Yang and
                  Chieh{-}Pu Lo and
                  Jaydeep P. Kulkarni},
  title        = {30.6 Vecim: {A} 289.13GOPS/W {RISC-V} Vector Co-Processor with Compute-in-Memory
                  Vector Register File for Efficient High-Performance Computing},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
                  San Francisco, CA, USA, February 18-22, 2024},
  pages        = {492--494},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ISSCC49657.2024.10454387},
  doi          = {10.1109/ISSCC49657.2024.10454387},
  timestamp    = {Tue, 19 Mar 2024 09:04:31 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/WangYLK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LeeLSLCLCLCKCWWWCWCC23,
  author       = {Po{-}Hao Lee and
                  Chia{-}Fu Lee and
                  Yi{-}Chun Shih and
                  Hon{-}Jarn Lin and
                  Yen{-}An Chang and
                  Cheng{-}Han Lu and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Chung{-}Chieh Chen and
                  Cheng{-}Hsiung Kuo and
                  Tan{-}Li Chou and
                  Chia{-}Yu Wang and
                  J. J. Wu and
                  Roger Wang and
                  Harry Chuang and
                  Yih Wang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {A 16nm 32Mb Embedded {STT-MRAM} with a 6ns Read-Access Time, a 1M-Cycle
                  Write Endurance, 20-Year Retention at 150{\textdegree}C and {MTJ-OTP}
                  Solutions for Magnetic Immunity},
  booktitle    = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
                  San Francisco, CA, USA, February 19-23, 2023},
  pages        = {494--495},
  publisher    = {{IEEE}},
  year         = {2023},
  url          = {https://doi.org/10.1109/ISSCC42615.2023.10067837},
  doi          = {10.1109/ISSCC42615.2023.10067837},
  timestamp    = {Wed, 29 Mar 2023 15:53:39 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeLSLCLCLCKCWWWCWCC23.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChiuCLHCXWKCHTL22,
  author       = {Yen{-}Cheng Chiu and
                  Tung{-}Cheng Chang and
                  Chun{-}Ying Lee and
                  Je{-}Min Hung and
                  Kuang{-}Tang Chang and
                  Cheng{-}Xin Xue and
                  Ssu{-}Yen Wu and
                  Hui{-}Yao Kao and
                  Peng Chen and
                  Hsiao{-}Yu Huang and
                  Shih{-}Hsih Teng and
                  Chieh{-}Pu Lo and
                  Yi{-}Chun Shih and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang and
                  Yier Jin and
                  Meng{-}Fan Chang},
  title        = {A 22-nm 1-Mb 1024-b Read Data-Protected {STT-MRAM} Macro With Near-Memory
                  Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware
                  Mobile Device},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {57},
  number       = {6},
  pages        = {1936--1949},
  year         = {2022},
  url          = {https://doi.org/10.1109/JSSC.2021.3112182},
  doi          = {10.1109/JSSC.2021.3112182},
  timestamp    = {Tue, 16 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChiuCLHCXWKCHTL22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChiuYTHCWCHLLCP22,
  author       = {Yen{-}Cheng Chiu and
                  Chia{-}Sheng Yang and
                  Shih{-}Hsih Teng and
                  Hsiao{-}Yu Huang and
                  Fu{-}Chun Chang and
                  Yuan Wu and
                  Yu{-}An Chien and
                  Fang{-}Ling Hsieh and
                  Chung{-}Yuan Li and
                  Guan{-}Yi Lin and
                  Po{-}Jung Chen and
                  Tsen{-}Hsiang Pan and
                  Chung{-}Chuan Lo and
                  Win{-}San Khwa and
                  Ren{-}Shuo Liu and
                  Chih{-}Cheng Hsieh and
                  Kea{-}Tiong Tang and
                  Chieh{-}Pu Lo and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang and
                  Meng{-}Fan Chang},
  title        = {A 22nm 4Mb {STT-MRAM} Data-Encrypted Near-Memory Computation Macro
                  with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b
                  {MAC} for {AI} Operations},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2022,
                  San Francisco, CA, USA, February 20-26, 2022},
  pages        = {178--180},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/ISSCC42614.2022.9731621},
  doi          = {10.1109/ISSCC42614.2022.9731621},
  timestamp    = {Tue, 20 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isscc/ChiuYTHCWCHLLCP22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChihLFSLNCLLMZS21,
  author       = {Yu{-}Der Chih and
                  Po{-}Hao Lee and
                  Hidehiro Fujiwara and
                  Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Rawan Naous and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Cheng{-}Han Lu and
                  Haruki Mori and
                  Wei{-}Cheng Zhao and
                  Dar Sun and
                  Mahmut E. Sinangil and
                  Yen{-}Huei Chen and
                  Tan{-}Li Chou and
                  Kerem Akarvardar and
                  Hung{-}Jen Liao and
                  Yih Wang and
                  Meng{-}Fan Chang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {An 89TOPS/W and 16.3TOPS/mm\({}^{\mbox{2}}\) All-Digital SRAM-Based
                  Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning
                  Edge Applications},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
                  San Francisco, CA, USA, February 13-22, 2021},
  pages        = {252--254},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/ISSCC42613.2021.9365766},
  doi          = {10.1109/ISSCC42613.2021.9365766},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChihLFSLNCLLMZS21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChihSLCLLCLSSCC20,
  author       = {Yu{-}Der Chih and
                  Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Chieh{-}Pu Lo and
                  Meng{-}Chun Shih and
                  Kuei{-}Hung Shen and
                  Harry Chuang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {13.3 {A} 22nm 32Mb Embedded {STT-MRAM} with 10ns Read Speed, 1M Cycle
                  Write Endurance, 10 Years Retention at 150{\textdegree}C and High
                  Immunity to Magnetic Field Interference},
  booktitle    = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
                  2020, San Francisco, CA, USA, February 16-20, 2020},
  pages        = {222--224},
  publisher    = {{IEEE}},
  year         = {2020},
  url          = {https://doi.org/10.1109/ISSCC19947.2020.9062955},
  doi          = {10.1109/ISSCC19947.2020.9062955},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChihSLCLLCLSSCC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LoLLLYCKLCCC19,
  author       = {Chieh{-}Pu Lo and
                  Wen{-}Zhang Lin and
                  Wei{-}Yu Lin and
                  Huan{-}Ting Lin and
                  Tzu{-}Hsien Yang and
                  Yen{-}Ning Chiang and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathon Chang and
                  Meng{-}Fan Chang},
  title        = {A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode
                  Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against
                  Resistance and Write-Delay Variation},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {2},
  pages        = {584--595},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2873588},
  doi          = {10.1109/JSSC.2018.2873588},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LoLLLYCKLCCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LeeLLCHWSYWKLLA17,
  author       = {Albert Lee and
                  Chieh{-}Pu Lo and
                  Chien{-}Chen Lin and
                  Wei{-}Hao Chen and
                  Kuo{-}Hsiang Hsu and
                  Zhibo Wang and
                  Fang Su and
                  Zhe Yuan and
                  Qi Wei and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Hochul Lee and
                  Pedram Khalili Amiri and
                  Kang{-}Lung Wang and
                  Yu Wang and
                  Huazhong Yang and
                  Yongpan Liu and
                  Meng{-}Fan Chang},
  title        = {A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme
                  for Frequent-OFF Fast-Wake-Up Nonvolatile Processors},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {8},
  pages        = {2194--2207},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2017.2700788},
  doi          = {10.1109/JSSC.2017.2700788},
  timestamp    = {Mon, 27 Mar 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/LeeLLCHWSYWKLLA17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/WangLLSLYLLCCLK17,
  author       = {Zhibo Wang and
                  Yongpan Liu and
                  Albert Lee and
                  Fang Su and
                  Chieh{-}Pu Lo and
                  Zhe Yuan and
                  Jinyang Li and
                  Chien{-}Chen Lin and
                  Wei{-}Hao Chen and
                  Hsiao{-}Yun Chiu and
                  Wei{-}En Lin and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Pedram Khalili Amiri and
                  Kang{-}Lung Wang and
                  Meng{-}Fan Chang and
                  Huazhong Yang},
  title        = {A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain
                  Adaption and Self-Write-Termination Achieving {\textgreater} 4{\texttimes}
                  Faster Clock Frequency and {\textgreater} 6{\texttimes} Higher Restore
                  Speed},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {10},
  pages        = {2769--2785},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2017.2724024},
  doi          = {10.1109/JSSC.2017.2724024},
  timestamp    = {Mon, 27 Mar 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/WangLLSLYLLCCLK17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LiuWLSLYLWWKLKW16,
  author       = {Yongpan Liu and
                  Zhibo Wang and
                  Albert Lee and
                  Fang Su and
                  Chieh{-}Pu Lo and
                  Zhe Yuan and
                  Chien{-}Chen Lin and
                  Qi Wei and
                  Yu Wang and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Pedram Khalili and
                  Kang{-}Lung Wang and
                  Meng{-}Fan Chang and
                  Huazhong Yang},
  title        = {4.7 {A} 65nm ReRAM-enabled nonvolatile processor with 6{\texttimes}
                  reduction in restore time and 4{\texttimes} higher clock frequency
                  using adaptive data retention and self-write-termination nonvolatile
                  logic},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {84--86},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417918},
  doi          = {10.1109/ISSCC.2016.7417918},
  timestamp    = {Mon, 27 Mar 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LiuWLSLYLWWKLKW16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/LinHLLCTYKLCC16,
  author       = {Chien{-}Chen Lin and
                  Jui{-}Yu Hung and
                  Wen{-}Zhang Lin and
                  Chieh{-}Pu Lo and
                  Yen{-}Ning Chiang and
                  Hsiang{-}Jen Tsai and
                  Geng{-}Hau Yang and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Tien{-}Fu Chen and
                  Meng{-}Fan Chang},
  title        = {7.4 {A} 256b-wordlength ReRAM-based {TCAM} with 1ns search-time and
                  14{\texttimes} improvement in wordlength-energyefficiency-density
                  product using 2.5T1R cell},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {136--137},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417944},
  doi          = {10.1109/ISSCC.2016.7417944},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LinHLLCTYKLCC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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