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BibTeX records: Igor Loi
@article{DBLP:journals/tvlsi/ChenLFTBR23, author = {Jie Chen and Igor Loi and Eric Flamand and Giuseppe Tagliavini and Luca Benini and Davide Rossi}, title = {Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {31}, number = {4}, pages = {456--469}, year = {2023}, url = {https://doi.org/10.1109/TVLSI.2022.3228336}, doi = {10.1109/TVLSI.2022.3228336}, timestamp = {Sun, 16 Apr 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/ChenLFTBR23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2309-01299, author = {Jie Chen and Igor Loi and Eric Flamand and Giuseppe Tagliavini and Luca Benini and Davide Rossi}, title = {Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters}, journal = {CoRR}, volume = {abs/2309.01299}, year = {2023}, url = {https://doi.org/10.48550/arXiv.2309.01299}, doi = {10.48550/ARXIV.2309.01299}, eprinttype = {arXiv}, eprint = {2309.01299}, timestamp = {Tue, 12 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2309-01299.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/RossiCEMTMGPLCF22, author = {Davide Rossi and Francesco Conti and Manuel Eggimann and Alfio Di Mauro and Giuseppe Tagliavini and Stefan Mach and Marco Guermandi and Antonio Pullini and Igor Loi and Jie Chen and Eric Flamand and Luca Benini}, title = {Vega: {A} Ten-Core SoC for IoT Endnodes With {DNN} Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode}, journal = {{IEEE} J. Solid State Circuits}, volume = {57}, number = {1}, pages = {127--139}, year = {2022}, url = {https://doi.org/10.1109/JSSC.2021.3114881}, doi = {10.1109/JSSC.2021.3114881}, timestamp = {Sat, 08 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/jssc/RossiCEMTMGPLCF22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isscc/RossiCEMMGTPLJF21, author = {Davide Rossi and Francesco Conti and Manuel Eggimann and Stefan Mach and Alfio Di Mauro and Marco Guermandi and Giuseppe Tagliavini and Antonio Pullini and Igor Loi and Jie Chen and Eric Flamand and Luca Benini}, title = {4.4 {A} 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7{\(\mu\)}W Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode}, booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021, San Francisco, CA, USA, February 13-22, 2021}, pages = {60--62}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/ISSCC42613.2021.9365939}, doi = {10.1109/ISSCC42613.2021.9365939}, timestamp = {Thu, 20 May 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isscc/RossiCEMMGTPLJF21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2110-09101, author = {Davide Rossi and Francesco Conti and Manuel Eggimann and Alfio Di Mauro and Giuseppe Tagliavini and Stefan Mach and Marco Guermandi and Antonio Pullini and Igor Loi and Jie Chen and Eric Flamand and Luca Benini}, title = {Vega: {A} 10-Core SoC for IoT End-Nodes with {DNN} Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode}, journal = {CoRR}, volume = {abs/2110.09101}, year = {2021}, url = {https://arxiv.org/abs/2110.09101}, eprinttype = {arXiv}, eprint = {2110.09101}, timestamp = {Fri, 22 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2110-09101.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/JieLBR20, author = {Jie Chen and Igor Loi and Luca Benini and Davide Rossi}, title = {Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core Cluster}, booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020}, pages = {1734--1739}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.23919/DATE48585.2020.9116212}, doi = {10.23919/DATE48585.2020.9116212}, timestamp = {Thu, 20 May 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/JieLBR20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/PulliniRLTB19, author = {Antonio Pullini and Davide Rossi and Igor Loi and Giuseppe Tagliavini and Luca Benini}, title = {Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing}, journal = {{IEEE} J. Solid State Circuits}, volume = {54}, number = {7}, pages = {1970--1981}, year = {2019}, url = {https://doi.org/10.1109/JSSC.2019.2912307}, doi = {10.1109/JSSC.2019.2912307}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/PulliniRLTB19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcas/PulliniCRLGB18, author = {Antonio Pullini and Francesco Conti and Davide Rossi and Igor Loi and Michael Gautschi and Luca Benini}, title = {A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing}, journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs}, volume = {65-II}, number = {8}, pages = {1094--1098}, year = {2018}, url = {https://doi.org/10.1109/TCSII.2017.2652982}, doi = {10.1109/TCSII.2017.2652982}, timestamp = {Wed, 27 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcas/PulliniCRLGB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tmscs/LoiCRMB18, author = {Igor Loi and Alessandro Capotondi and Davide Rossi and Andrea Marongiu and Luca Benini}, title = {The Quest for Energy-Efficient I{\textdollar} Design in Ultra-Low-Power Clustered Many-Cores}, journal = {{IEEE} Trans. Multi Scale Comput. Syst.}, volume = {4}, number = {2}, pages = {99--112}, year = {2018}, url = {https://doi.org/10.1109/TMSCS.2017.2769046}, doi = {10.1109/TMSCS.2017.2769046}, timestamp = {Wed, 02 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tmscs/LoiCRMB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tpds/AzarkhishRLB18, author = {Erfan Azarkhish and Davide Rossi and Igor Loi and Luca Benini}, title = {Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes}, journal = {{IEEE} Trans. Parallel Distributed Syst.}, volume = {29}, number = {2}, pages = {420--434}, year = {2018}, url = {https://doi.org/10.1109/TPDS.2017.2752706}, doi = {10.1109/TPDS.2017.2752706}, timestamp = {Fri, 02 Oct 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tpds/AzarkhishRLB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asap/FlamandR0LPRB18, author = {Eric Flamand and Davide Rossi and Francesco Conti and Igor Loi and Antonio Pullini and Florent Rotenberg and Luca Benini}, title = {{GAP-8:} {A} {RISC-V} SoC for {AI} at the Edge of the IoT}, booktitle = {29th {IEEE} International Conference on Application-specific Systems, Architectures and Processors, {ASAP} 2018, Milano, Italy, July 10-12, 2018}, pages = {1--4}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/ASAP.2018.8445101}, doi = {10.1109/ASAP.2018.8445101}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/asap/FlamandR0LPRB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/esscirc/PulliniRLMB18, author = {Antonio Pullini and Davide Rossi and Igor Loi and Alfio Di Mauro and Luca Benini}, title = {Mr. Wolf: {A} 1 GFLOP/s Energy-Proportional Parallel Ultra Low Power SoC for {IOT} Edge Processing}, booktitle = {44th {IEEE} European Solid State Circuits Conference, {ESSCIRC} 2018, Dresden, Germany, September 3-6, 2018}, pages = {274--277}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/ESSCIRC.2018.8494247}, doi = {10.1109/ESSCIRC.2018.8494247}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/esscirc/PulliniRLMB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/DazziPRBLBB18, author = {Martino Dazzi and Pierpaolo Palestri and Davide Rossi and Andrea Bandiziol and Igor Loi and David E. Bellasi and Luca Benini}, title = {Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes}, booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018, 27-30 May 2018, Florence, Italy}, pages = {1--5}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/ISCAS.2018.8351893}, doi = {10.1109/ISCAS.2018.8351893}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iscas/DazziPRBLBB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/RossiLPMBCBF17, author = {Davide Rossi and Igor Loi and Antonio Pullini and Thomas Christoph M{\"{u}}ller and Andreas Burg and Francesco Conti and Luca Benini and Philippe Flatresse}, title = {A Self-Aware Architecture for {PVT} Compensation and Power Nap in Near Threshold Processors}, journal = {{IEEE} Des. Test}, volume = {34}, number = {6}, pages = {46--53}, year = {2017}, url = {https://doi.org/10.1109/MDAT.2017.2750907}, doi = {10.1109/MDAT.2017.2750907}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/dt/RossiLPMBCBF17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/esl/PayamiALB17, author = {Maryam Payami and Erfan Azarkhish and Igor Loi and Luca Benini}, title = {A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters}, journal = {{IEEE} Embed. Syst. Lett.}, volume = {9}, number = {4}, pages = {125--128}, year = {2017}, url = {https://doi.org/10.1109/LES.2017.2707978}, doi = {10.1109/LES.2017.2707978}, timestamp = {Thu, 10 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/esl/PayamiALB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/RossiPLGGTCBPBC17, author = {Davide Rossi and Antonio Pullini and Igor Loi and Michael Gautschi and Frank Kagan G{\"{u}}rkaynak and Adam Teman and Jeremy Constantin and Andreas Burg and Ivan Miro Panades and Edith Beign{\'{e}} and Fabien Clermidy and Philippe Flatresse and Luca Benini}, title = {Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster}, journal = {{IEEE} Micro}, volume = {37}, number = {5}, pages = {20--31}, year = {2017}, url = {https://doi.org/10.1109/MM.2017.3711645}, doi = {10.1109/MM.2017.3711645}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/RossiPLGGTCBPBC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcas/ContiSSPRGMGLHM17, author = {Francesco Conti and Robert Schilling and Pasquale Davide Schiavone and Antonio Pullini and Davide Rossi and Frank Kagan G{\"{u}}rkaynak and Michael Muehlberghuber and Michael Gautschi and Igor Loi and Germain Haugou and Stefan Mangard and Luca Benini}, title = {An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics}, journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.}, volume = {64-I}, number = {9}, pages = {2481--2494}, year = {2017}, url = {https://doi.org/10.1109/TCSI.2017.2698019}, doi = {10.1109/TCSI.2017.2698019}, timestamp = {Fri, 22 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcas/ContiSSPRGMGLHM17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/AzarkhishPRLB17, author = {Erfan Azarkhish and Christoph Pfister and Davide Rossi and Igor Loi and Luca Benini}, title = {Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {25}, number = {1}, pages = {210--223}, year = {2017}, url = {https://doi.org/10.1109/TVLSI.2016.2570283}, doi = {10.1109/TVLSI.2016.2570283}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/AzarkhishPRLB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GautschiSTLPRFG17, author = {Michael Gautschi and Pasquale Davide Schiavone and Andreas Traber and Igor Loi and Antonio Pullini and Davide Rossi and Eric Flamand and Frank K. G{\"{u}}rkaynak and Luca Benini}, title = {Near-Threshold {RISC-V} Core With {DSP} Extensions for Scalable IoT Endpoint Devices}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {25}, number = {10}, pages = {2700--2713}, year = {2017}, url = {https://doi.org/10.1109/TVLSI.2017.2654506}, doi = {10.1109/TVLSI.2017.2654506}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GautschiSTLPRFG17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/AzarkhishRLB17, author = {Erfan Azarkhish and Davide Rossi and Igor Loi and Luca Benini}, title = {Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes}, journal = {CoRR}, volume = {abs/1701.06420}, year = {2017}, url = {http://arxiv.org/abs/1701.06420}, eprinttype = {arXiv}, eprint = {1701.06420}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/AzarkhishRLB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/mam/TuveriMPSLCR16, author = {Giuseppe Tuveri and Paolo Meloni and Francesca Palumbo and Giovanni Pietro Seu and Igor Loi and Francesco Conti and Luigi Raffo}, title = {On-the-fly adaptivity for process networks over shared-memory platforms}, journal = {Microprocess. Microsystems}, volume = {46}, pages = {240--254}, year = {2016}, url = {https://doi.org/10.1016/j.micpro.2016.06.010}, doi = {10.1016/J.MICPRO.2016.06.010}, timestamp = {Sat, 22 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/mam/TuveriMPSLCR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsisp/0001RPLB16, author = {Francesco Conti and Davide Rossi and Antonio Pullini and Igor Loi and Luca Benini}, title = {{PULP:} {A} Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision}, journal = {J. Signal Process. Syst.}, volume = {84}, number = {3}, pages = {339--354}, year = {2016}, url = {https://doi.org/10.1007/s11265-015-1070-9}, doi = {10.1007/S11265-015-1070-9}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/vlsisp/0001RPLB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/arcs/AzarkhishRLB16, author = {Erfan Azarkhish and Davide Rossi and Igor Loi and Luca Benini}, editor = {Frank Hannig and Jo{\~{a}}o M. P. Cardoso and Thilo Pionteck and Dietmar Fey and Wolfgang Schr{\"{o}}der{-}Preikschat and J{\"{u}}rgen Teich}, title = {Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube}, booktitle = {Architecture of Computing Systems - {ARCS} 2016 - 29th International Conference, Nuremberg, Germany, April 4-7, 2016, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {9637}, pages = {19--31}, publisher = {Springer}, year = {2016}, url = {https://doi.org/10.1007/978-3-319-30695-7\_2}, doi = {10.1007/978-3-319-30695-7\_2}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/arcs/AzarkhishRLB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cd/MeloniD0LRB16, author = {Paolo Meloni and Gianfranco Deriu and Francesco Conti and Igor Loi and Luigi Raffo and Luca Benini}, editor = {Gianluca Palermo and John Feo}, title = {Curbing the roofline: a scalable and flexible architecture for CNNs on {FPGA}}, booktitle = {Proceedings of the {ACM} International Conference on Computing Frontiers, CF'16, Como, Italy, May 16-19, 2016}, pages = {376--383}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2903150.2911715}, doi = {10.1145/2903150.2911715}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cd/MeloniD0LRB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/coolchips/RossiPLGGTCBPBC16, author = {Davide Rossi and Antonio Pullini and Igor Loi and Michael Gautschi and Frank Kagan G{\"{u}}rkaynak and Adam Teman and Jeremy Constantin and Andreas Burg and Ivan Miro Panades and Edith Beign{\'{e}} and Fabien Clermidy and Fady Abouzeid and Philippe Flatresse and Luca Benini}, title = {193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing}, booktitle = {2016 {IEEE} Symposium in Low-Power and High-Speed Chips, {COOL} {CHIPS} XIX, Yokohama, Japan, April 20-22, 2016}, pages = {1--3}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/CoolChips.2016.7503670}, doi = {10.1109/COOLCHIPS.2016.7503670}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/coolchips/RossiPLGGTCBPBC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/Pullini0RLGB16, author = {Antonio Pullini and Francesco Conti and Davide Rossi and Igor Loi and Michael Gautschi and Luca Benini}, title = {A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision}, booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016, Montr{\'{e}}al, QC, Canada, May 22-25, 2016}, pages = {2910}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ISCAS.2016.7539213}, doi = {10.1109/ISCAS.2016.7539213}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iscas/Pullini0RLGB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/MeloniD0LRB16, author = {Paolo Meloni and Gianfranco Deriu and Francesco Conti and Igor Loi and Luigi Raffo and Luca Benini}, editor = {Peter M. Athanas and Ren{\'{e}} Cumplido and Claudia Feregrino and Ron Sass}, title = {A high-efficiency runtime reconfigurable {IP} for {CNN} acceleration on a mid-range all-programmable SoC}, booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016}, pages = {1--8}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/ReConFig.2016.7857144}, doi = {10.1109/RECONFIG.2016.7857144}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/reconfig/MeloniD0LRB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/GautschiSTLPRFG16, author = {Michael Gautschi and Pasquale Davide Schiavone and Andreas Traber and Igor Loi and Antonio Pullini and Davide Rossi and Eric Flamand and Frank K. G{\"{u}}rkaynak and Luca Benini}, title = {A near-threshold {RISC-V} core with {DSP} extensions for scalable IoT Endpoint Devices}, journal = {CoRR}, volume = {abs/1608.08376}, year = {2016}, url = {http://arxiv.org/abs/1608.08376}, eprinttype = {arXiv}, eprint = {1608.08376}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/GautschiSTLPRFG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/0001SSPRGMGLHMB16, author = {Francesco Conti and Robert Schilling and Pasquale Davide Schiavone and Antonio Pullini and Davide Rossi and Frank Kagan G{\"{u}}rkaynak and Michael Muehlberghuber and Michael Gautschi and Igor Loi and Germain Haugou and Stefan Mangard and Luca Benini}, title = {An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics}, journal = {CoRR}, volume = {abs/1612.05974}, year = {2016}, url = {http://arxiv.org/abs/1612.05974}, eprinttype = {arXiv}, eprint = {1612.05974}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/0001SSPRGMGLHMB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/AzarkhishRLB15, author = {Erfan Azarkhish and Davide Rossi and Igor Loi and Luca Benini}, title = {A Modular Shared {L2} Memory Design for 3-D Integration}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {8}, pages = {1485--1498}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2340013}, doi = {10.1109/TVLSI.2014.2340013}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/AzarkhishRLB15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cf/LoiRHGB15, author = {Igor Loi and Davide Rossi and Germain Haugou and Michael Gautschi and Luca Benini}, editor = {Claudia Di Napoli and Valentina Salapura and Hubertus Franke and Rui Hou}, title = {Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters}, booktitle = {Proceedings of the 12th {ACM} International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015}, pages = {64:1--64:8}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2742854.2747288}, doi = {10.1145/2742854.2747288}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cf/LoiRHGB15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/AzarkhishRLB15, author = {Erfan Azarkhish and Davide Rossi and Igor Loi and Luca Benini}, editor = {Wolfgang Nebel and David Atienza}, title = {High performance {AXI-4.0} based interconnect for extensible smart memory cubes}, booktitle = {Proceedings of the 2015 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2015, Grenoble, France, March 9-13, 2015}, pages = {1317--1322}, publisher = {{ACM}}, year = {2015}, url = {http://dl.acm.org/citation.cfm?id=2757119}, timestamp = {Mon, 09 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/date/AzarkhishRLB15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hotchips/Rossi0MPLGTCFB15, author = {Davide Rossi and Francesco Conti and Andrea Marongiu and Antonio Pullini and Igor Loi and Michael Gautschi and Giuseppe Tagliavini and Alessandro Capotondi and Philippe Flatresse and Luca Benini}, title = {{PULP:} {A} parallel ultra low power platform for next generation IoT applications}, booktitle = {2015 {IEEE} Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015}, pages = {1--39}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477325}, doi = {10.1109/HOTCHIPS.2015.7477325}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hotchips/Rossi0MPLGTCFB15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cf/RossiLHB14, author = {Davide Rossi and Igor Loi and Germain Haugou and Luca Benini}, editor = {Pedro Trancoso and Diana Franklin and Sally A. McKee}, title = {Ultra-low-latency lightweight {DMA} for tightly coupled multi-core clusters}, booktitle = {Computing Frontiers Conference, CF'14, Cagliari, Italy - May 20 - 22, 2014}, pages = {15:1--15:10}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2597917.2597922}, doi = {10.1145/2597917.2597922}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cf/RossiLHB14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LoiB14, author = {Igor Loi and Luca Benini}, editor = {Gerhard P. Fettweis and Wolfgang Nebel}, title = {A multi banked - Multi ported - Non blocking shared {L2} cache for MPSoC platforms}, booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2014, Dresden, Germany, March 24-28, 2014}, pages = {1--6}, publisher = {European Design and Automation Association}, year = {2014}, url = {https://doi.org/10.7873/DATE.2014.093}, doi = {10.7873/DATE.2014.093}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/date/LoiB14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/MeloniTRLC14, author = {Paolo Meloni and Giuseppe Tuveri and Luigi Raffo and Igor Loi and Francesco Conti}, editor = {Masoud Daneshtalab and Masoumeh Ebrahimi and Maurizio Palesi and Federico Angiolini and Juha Plosila}, title = {A Stream Buffer Mechanism for Pervasive Splitting Transformations on Polyhedral Process Networks}, booktitle = {Proceedings of the 2nd International Workshop on Many-core Embedded Systems, MES'2014, in conjunction with the 41st International Symposium on Computer Architecture, ISCA'2014, Minneapolis, MN, USA, June 15, 2014}, pages = {25--32}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2613908.2613913}, doi = {10.1145/2613908.2613913}, timestamp = {Thu, 15 Jun 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/isca/MeloniTRLC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/meco/MeloniTRLC14, author = {Paolo Meloni and Giuseppe Tuveri and Luigi Raffo and Igor Loi and Francesco Conti}, title = {Online process transformation for polyhedral process networks in shared-memory MPSoCs}, booktitle = {3rd Mediterranean Conference on Embedded Computing, {MECO} 2014, Budva, Montenegro, June 15-19, 2014}, pages = {92--97}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/MECO.2014.6862666}, doi = {10.1109/MECO.2014.6862666}, timestamp = {Mon, 08 Feb 2021 13:26:44 +0100}, biburl = {https://dblp.org/rec/conf/meco/MeloniTRLC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sips/0001RPLB14, author = {Francesco Conti and Davide Rossi and Antonio Pullini and Igor Loi and Luca Benini}, title = {Energy-efficient vision on the {PULP} platform for ultra-low power parallel computing}, booktitle = {2014 {IEEE} Workshop on Signal Processing Systems, SiPS 2014, Belfast, United Kingdom, October 20-22, 2014}, pages = {274--279}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/SiPS.2014.6986099}, doi = {10.1109/SIPS.2014.6986099}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sips/0001RPLB14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/iet-cdt/AzarkhishLB13, author = {Erfan Azarkhish and Igor Loi and Luca Benini}, title = {A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects}, journal = {{IET} Comput. Digit. Tech.}, volume = {7}, number = {5}, pages = {191--199}, year = {2013}, url = {https://doi.org/10.1049/iet-cdt.2013.0031}, doi = {10.1049/IET-CDT.2013.0031}, timestamp = {Tue, 14 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/iet-cdt/AzarkhishLB13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WeisLBW13, author = {Christian Weis and Igor Loi and Luca Benini and Norbert Wehn}, title = {Exploration and Optimization of 3-D Integrated {DRAM} Subsystems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {32}, number = {4}, pages = {597--610}, year = {2013}, url = {https://doi.org/10.1109/TCAD.2012.2235125}, doi = {10.1109/TCAD.2012.2235125}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WeisLBW13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/3dic/AzarkhishLB13, author = {Erfan Azarkhish and Igor Loi and Luca Benini}, title = {A high-performance multiported {L2} memory {IP} for scalable three-dimensional integration}, booktitle = {2013 {IEEE} International 3D Systems Integration Conference (3DIC), San Francisco, CA, USA, October 2-4, 2013}, pages = {1--8}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/3DIC.2013.6702347}, doi = {10.1109/3DIC.2013.6702347}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/3dic/AzarkhishLB13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cf/KakoeeLB13, author = {Mohammad Reza Kakoee and Igor Loi and Luca Benini}, editor = {Hubertus Franke and Alexander Heinecke and Krishna V. Palem and Eli Upfal}, title = {A shared-FPU architecture for ultra-low power MPSoCs}, booktitle = {Computing Frontiers Conference, CF'13, Ischia, Italy, May 14 - 16, 2013}, pages = {3:1--3:8}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2482767.2482772}, doi = {10.1145/2482767.2482772}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/cf/KakoeeLB13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/nocs/AzarkhishLB13, author = {Erfan Azarkhish and Igor Loi and Luca Benini}, title = {3D logarithmic interconnect: Stacking multiple {L1} memory dies over multi-core clusters}, booktitle = {2013 Seventh {IEEE/ACM} International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013}, pages = {1--2}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/NoCS.2013.6558394}, doi = {10.1109/NOCS.2013.6558394}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/nocs/AzarkhishLB13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcas/KakoeeLB12, author = {Mohammad Reza Kakoee and Igor Loi and Luca Benini}, title = {Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters}, journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs}, volume = {59-II}, number = {12}, pages = {927--931}, year = {2012}, url = {https://doi.org/10.1109/TCSII.2012.2231039}, doi = {10.1109/TCSII.2012.2231039}, timestamp = {Wed, 27 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcas/KakoeeLB12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/KakoeeLB12, author = {Mohammad Reza Kakoee and Igor Loi and Luca Benini}, editor = {Wolfgang Rosenstiel and Lothar Thiele}, title = {A resilient architecture for low latency communication in shared-L1 processor clusters}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, pages = {887--892}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/DATE.2012.6176623}, doi = {10.1109/DATE.2012.6176623}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/KakoeeLB12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/WeisLBW12, author = {Christian Weis and Igor Loi and Luca Benini and Norbert Wehn}, editor = {Wolfgang Rosenstiel and Lothar Thiele}, title = {An energy efficient {DRAM} subsystem for 3D integrated SoCs}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, pages = {1138--1141}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/DATE.2012.6176668}, doi = {10.1109/DATE.2012.6176668}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/WeisLBW12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsi/BeanatoLMLB12, author = {Giulia Beanato and Igor Loi and Giovanni De Micheli and Yusuf Leblebici and Luca Benini}, editor = {Srinivas Katkoori and Matthew R. Guthaus and Ayse K. Coskun and Andreas Burg and Ricardo Reis}, title = {3D-LIN: {A} configurable low-latency interconnect for multi-core clusters with 3D stacked {L1} memory}, booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012}, pages = {30--35}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/VLSI-SoC.2012.6379001}, doi = {10.1109/VLSI-SOC.2012.6379001}, timestamp = {Tue, 06 Sep 2022 16:02:54 +0200}, biburl = {https://dblp.org/rec/conf/vlsi/BeanatoLMLB12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsi/BeanatoLMLB12a, author = {Giulia Beanato and Igor Loi and Giovanni De Micheli and Yusuf Leblebici and Luca Benini}, editor = {Andreas Burg and Ayse K. Coskun and Matthew R. Guthaus and Srinivas Katkoori and Ricardo Reis}, title = {Configurable Low-Latency Interconnect for Multi-core Clusters}, booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design - 20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012, Revised Selected Papers}, series = {{IFIP} Advances in Information and Communication Technology}, volume = {418}, pages = {107--124}, publisher = {Springer}, year = {2012}, url = {https://doi.org/10.1007/978-3-642-45073-0\_6}, doi = {10.1007/978-3-642-45073-0\_6}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsi/BeanatoLMLB12a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/PlasLLMOTTLSKVCVSWLPBMCROPBORWDNAPABDTBM11, author = {Geert Van der Plas and Paresh Limaye and Igor Loi and Abdelkarim Mercha and Herman Oprins and Cristina Torregiani and Steven Thijs and Dimitri Linten and Michele Stucchi and Guruprasad Katti and Dimitrios Velenis and Vladimir Cherman and Bart Vandevelde and Veerle Simons and Ingrid De Wolf and Riet Labie and Dan Perry and Stephane Bronckers and Nikolaos Minas and Miro Cupac and Wouter Ruythooren and Jan Van Olmen and Alain Phommahaxay and Muriel de Potter de ten Broeck and Ann Opdebeeck and Michal Rakowski and Bart De Wachter and Morin Dehan and Marc Nelis and Rahul Agarwal and Antonio Pullini and Federico Angiolini and Luca Benini and Wim Dehaene and Youssef Travaly and Eric Beyne and Paul Marchal}, title = {Design Issues and Considerations for Low-Cost 3-D {TSV} {IC} Technology}, journal = {{IEEE} J. Solid State Circuits}, volume = {46}, number = {1}, pages = {293--307}, year = {2011}, url = {https://doi.org/10.1109/JSSC.2010.2074070}, doi = {10.1109/JSSC.2010.2074070}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/PlasLLMOTTLSKVCVSWLPBMCROPBORWDNAPABDTBM11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LoiAFMB11, author = {Igor Loi and Federico Angiolini and Shinobu Fujita and Subhasish Mitra and Luca Benini}, title = {Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {30}, number = {1}, pages = {124--134}, year = {2011}, url = {https://doi.org/10.1109/TCAD.2010.2065990}, doi = {10.1109/TCAD.2010.2065990}, timestamp = {Sun, 25 Jul 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LoiAFMB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/WeisWLB11, author = {Christian Weis and Norbert Wehn and Igor Loi and Luca Benini}, title = {Design space exploration for 3D-stacked DRAMs}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, pages = {389--394}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/DATE.2011.5763068}, doi = {10.1109/DATE.2011.5763068}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/WeisWLB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/RahimiLKB11, author = {Abbas Rahimi and Igor Loi and Mohammad Reza Kakoee and Luca Benini}, title = {A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, pages = {491--496}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/DATE.2011.5763085}, doi = {10.1109/DATE.2011.5763085}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/RahimiLKB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/patmos/DoganABLB11, author = {Ahmed Yasir Dogan and David Atienza and Andreas Burg and Igor Loi and Luca Benini}, editor = {Jos{\'{e}} L. Ayala and Braulio Garc{\'{\i}}a{-}C{\'{a}}mara and Manuel Prieto and Martino Ruggiero and Gilles Sicard}, title = {Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing}, booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, {PATMOS} 2011, Madrid, Spain, September 26-29, 2011. Proceedings}, series = {Lecture Notes in Computer Science}, volume = {6951}, pages = {102--111}, publisher = {Springer}, year = {2011}, url = {https://doi.org/10.1007/978-3-642-24154-3\_11}, doi = {10.1007/978-3-642-24154-3\_11}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/patmos/DoganABLB11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LoiB10, author = {Igor Loi and Luca Benini}, editor = {Giovanni De Micheli and Bashir M. Al{-}Hashimi and Wolfgang M{\"{u}}ller and Enrico Macii}, title = {An efficient distributed memory interface for many-core platform with 3D stacked {DRAM}}, booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany, March 8-12, 2010}, pages = {99--104}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/DATE.2010.5457230}, doi = {10.1109/DATE.2010.5457230}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/LoiB10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/KakoeeLB10, author = {Mohammad Reza Kakoee and Igor Loi and Luca Benini}, editor = {R. Iris Bahar and Fabrizio Lombardi and David Atienza and Erik Brunvand}, title = {A new physical routing approach for robust bundled signaling on NoC links}, booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009, Providence, Rhode Island, USA, May 16-18 2010}, pages = {3--8}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1785481.1785485}, doi = {10.1145/1785481.1785485}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/KakoeeLB10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/LoiMPB10, author = {Igor Loi and Pol Marchal and Antonio Pullini and Luca Benini}, title = {3D NoCs - Unifying inter {\&} intra chip communication}, booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May 30 - June 2, 2010, Paris, France}, pages = {3337--3340}, publisher = {{IEEE}}, year = {2010}, url = {https://doi.org/10.1109/ISCAS.2010.5537895}, doi = {10.1109/ISCAS.2010.5537895}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iscas/LoiMPB10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LoiAB09, author = {Igor Loi and Federico Angiolini and Luca Benini}, editor = {Luca Benini and Giovanni De Micheli and Bashir M. Al{-}Hashimi and Wolfgang M{\"{u}}ller}, title = {Synthesis of low-overhead configurable source routing tables for network interfaces}, booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France, April 20-24, 2009}, pages = {262--267}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/DATE.2009.5090668}, doi = {10.1109/DATE.2009.5090668}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/date/LoiAB09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/LoiAB08, author = {Igor Loi and Federico Angiolini and Luca Benini}, editor = {Donatella Sciuto}, title = {Developing Mesochronous Synchronizers to Enable 3D NoCs}, booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany, March 10-14, 2008}, pages = {1414--1419}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1109/DATE.2008.4484872}, doi = {10.1109/DATE.2008.4484872}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/LoiAB08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/LoiMLFB08, author = {Igor Loi and Subhasish Mitra and Thomas H. Lee and Shinobu Fujita and Luca Benini}, editor = {Sani R. Nassif and Jaijeet S. Roychowdhury}, title = {A low-overhead fault tolerance scheme for TSV-based 3D network on chip links}, booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008, San Jose, CA, USA, November 10-13, 2008}, pages = {598--602}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ICCAD.2008.4681638}, doi = {10.1109/ICCAD.2008.4681638}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/LoiMLFB08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/vlsi/MeloniLACBRB07, author = {Paolo Meloni and Igor Loi and Federico Angiolini and Salvatore Carta and Massimo Barbaro and Luigi Raffo and Luca Benini}, title = {Area and Power Modeling for Networks-on-Chip with Layout Awareness}, journal = {{VLSI} Design}, volume = {2007}, pages = {50285:1--50285:12}, year = {2007}, url = {https://doi.org/10.1155/2007/50285}, doi = {10.1155/2007/50285}, timestamp = {Fri, 27 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/vlsi/MeloniLACBRB07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/nanonet/LoiAB07, author = {Igor Loi and Federico Angiolini and Luca Benini}, editor = {Salvatore Coffa}, title = {Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow}, booktitle = {2nd Internationa {ICST} Conference on Nano-Networks, Nano-Net 2007, Catania, Italy, September 24-26, 2007}, pages = {15}, publisher = {{ICST/ACM}}, year = {2007}, url = {https://doi.org/10.4108/ICST.NANONET2007.2033}, doi = {10.4108/ICST.NANONET2007.2033}, timestamp = {Fri, 26 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/nanonet/LoiAB07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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