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ORCIDBibTeX records: Yuchun Ma
@article{DBLP:journals/trets/ZhaoMHZXB23,
author = {Kang Zhao and
Yuchun Ma and
Ruining He and
Jixing Zhang and
Ning Xu and
Jinian Bian},
title = {Adaptive Selection and Clustering of Partial Reconfiguration Modules
for Modern {FPGA} Design Flow},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {27:1--27:24},
year = {2023},
url = {https://doi.org/10.1145/3567427},
doi = {10.1145/3567427},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhaoMHZXB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetci/MaMLJCG22,
author = {Lijia Ma and
Yuchun Ma and
Qiuzhen Lin and
Junkai Ji and
Carlos A. Coello Coello and
Maoguo Gong},
title = {{SNEGAN:} Signed Network Embedding by Using Generative Adversarial
Nets},
journal = {{IEEE} Trans. Emerg. Top. Comput. Intell.},
volume = {6},
number = {1},
pages = {136--149},
year = {2022},
url = {https://doi.org/10.1109/TETCI.2020.3035937},
doi = {10.1109/TETCI.2020.3035937},
timestamp = {Tue, 08 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tetci/MaMLJCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/wacv/HeLZM19,
author = {Yihui He and
Xianggen Liu and
Huasong Zhong and
Yuchun Ma},
title = {AddressNet: Shift-Based Primitives for Efficient Convolutional Neural
Networks},
booktitle = {{IEEE} Winter Conference on Applications of Computer Vision, {WACV}
2019, Waikoloa Village, HI, USA, January 7-11, 2019},
pages = {1213--1222},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/WACV.2019.00134},
doi = {10.1109/WACV.2019.00134},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/wacv/HeLZM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YuFSGMT18,
author = {Teng Yu and
Bo Feng and
Mark Stillwell and
Liucheng Guo and
Yuchun Ma and
John Thomson},
title = {Lattice-Based Scheduling for Multi-FPGA Systems},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2018,
Naha, Okinawa, Japan, December 10-14, 2018},
pages = {318--321},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/FPT.2018.00063},
doi = {10.1109/FPT.2018.00063},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YuFSGMT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1809-08458,
author = {Huasong Zhong and
Xianggen Liu and
Yihui He and
Yuchun Ma},
title = {Shift-based Primitives for Efficient Convolutional Neural Networks},
journal = {CoRR},
volume = {abs/1809.08458},
year = {2018},
url = {http://arxiv.org/abs/1809.08458},
eprinttype = {arXiv},
eprint = {1809.08458},
timestamp = {Fri, 05 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1809-08458.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsjkx/YangMH018,
author = {Fei Yang and
Yuchun Ma and
Jin Hou and
Ning Xu},
title = {{\unicode{22522}}{\unicode{20110}}MPSoC{\unicode{24182}}{\unicode{34892}}{\unicode{35843}}{\unicode{24230}}{\unicode{30340}}{\unicode{30697}}{\unicode{38453}}{\unicode{20056}}{\unicode{27861}}{\unicode{21152}}{\unicode{36895}}{\unicode{31639}}{\unicode{27861}}{\unicode{30740}}{\unicode{31350}}
(Research on Acceleration of Matrix Multiplication Based on Parallel
Scheduling on MPSoC)},
journal = {{\unicode{35745}}{\unicode{31639}}{\unicode{26426}}{\unicode{31185}}{\unicode{23398}}},
volume = {44},
number = {8},
pages = {36--41},
year = {2017},
url = {https://doi.org/10.11896/j.issn.1002-137X.2017.08.007},
doi = {10.11896/J.ISSN.1002-137X.2017.08.007},
timestamp = {Fri, 20 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsjkx/YangMH018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/edm/MaM17,
author = {Lin Ma and
Yuchun Ma},
editor = {Xiangen Hu and
Tiffany Barnes and
Arnon Hershkovitz and
Luc Paquette},
title = {Intelligent Composition of Test Papers based on {MOOC} Learning Data},
booktitle = {Proceedings of the 10th International Conference on Educational Data
Mining, {EDM} 2017, Wuhan, Hubei, China, June 25-28, 2017},
publisher = {International Educational Data Mining Society {(IEDMS)}},
year = {2017},
url = {http://educationaldatamining.org/EDM2017/proc\_files/papers/paper\_56.pdf},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/edm/MaM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/ZhaoFLYWFMY16,
author = {Wenlai Zhao and
Haohuan Fu and
Wayne Luk and
Teng Yu and
Shaojun Wang and
Bo Feng and
Yuchun Ma and
Guangwen Yang},
title = {{F-CNN:} An FPGA-based framework for training Convolutional Neural
Networks},
booktitle = {27th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2016, London, United Kingdom,
July 6-8, 2016},
pages = {107--114},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ASAP.2016.7760779},
doi = {10.1109/ASAP.2016.7760779},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/ZhaoFLYWFMY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/YuFSCZLLWM16,
author = {Teng Yu and
Bo Feng and
Mark Stillwell and
Jos{\'{e}} Gabriel F. Coutinho and
Wenlai Zhao and
Shuang Liang and
Wayne Luk and
Alexander L. Wolf and
Yuchun Ma},
title = {Relation-oriented resource allocation for multi-accelerator systems},
booktitle = {27th {IEEE} International Conference on Application-specific Systems,
Architectures and Processors, {ASAP} 2016, London, United Kingdom,
July 6-8, 2016},
pages = {243--244},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ASAP.2016.7760809},
doi = {10.1109/ASAP.2016.7760809},
timestamp = {Thu, 22 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/YuFSCZLLWM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/MaoZFHM16,
author = {Fubing Mao and
Wei Zhang and
Bo Feng and
Bingsheng He and
Yuchun Ma},
editor = {Ayse K. Coskun and
Martin Margala and
Laleh Behjat and
Jie Han},
title = {Modular Placement for Interposer based Multi-FPGA Systems},
booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI,
{GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016},
pages = {93--98},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2902961.2903025},
doi = {10.1145/2902961.2903025},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/MaoZFHM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuWCMXY15,
author = {Wulong Liu and
Yu Wang and
Guoqing Chen and
Yuchun Ma and
Yuan Xie and
Huazhong Yang},
title = {Whitespace-Aware {TSV} Arrangement in 3-D Clock Tree Synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {9},
pages = {1842--1853},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2354347},
doi = {10.1109/TVLSI.2014.2354347},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuWCMXY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangYTCMSY15,
author = {Yu Wang and
Song Yao and
Shuai Tao and
Xiaoming Chen and
Yuchun Ma and
Yiyu Shi and
Huazhong Yang},
title = {{HS3-DPG:} Hierarchical Simulation for 3-D {P/G} Network},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {10},
pages = {2307--2311},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2358582},
doi = {10.1109/TVLSI.2014.2358582},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangYTCMSY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/ZhangML15,
author = {Chao Zhang and
Yuchun Ma and
Wayne Luk},
title = {{HW/SW} Partitioning Algorithm Targeting {MPSOC} with Dynamic Partial
Reconfigurable Fabric},
booktitle = {14th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2015, Xi'an, China, August 26-28, 2015},
pages = {240--241},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CADGRAPHICS.2015.49},
doi = {10.1109/CADGRAPHICS.2015.49},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/cadgraphics/ZhangML15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/LiuWMXY14,
author = {Wulong Liu and
Yu Wang and
Yuchun Ma and
Yuan Xie and
Huazhong Yang},
title = {On-Chip Hybrid Power Supply System for Wireless Sensor Nodes},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {10},
number = {3},
pages = {23:1--23:22},
year = {2014},
url = {https://doi.org/10.1145/2492683},
doi = {10.1145/2492683},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/LiuWMXY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/WangGGMW14,
author = {Wenqiang Wang and
Kaiyuan Guo and
Mengyuan Gu and
Yuchun Ma and
Yu Wang},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {A universal FPGA-based floating-point matrix processor for mobile
systems},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {139--146},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082766},
doi = {10.1109/FPT.2014.7082766},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/WangGGMW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/MaLZL14,
author = {Yuchun Ma and
Jinglan Liu and
Chao Zhang and
Wayne Luk},
title = {{HW/SW} partitioning for region-based dynamic partial reconfigurable
FPGAs},
booktitle = {32nd {IEEE} International Conference on Computer Design, {ICCD} 2014,
Seoul, South Korea, October 19-22, 2014},
pages = {470--476},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICCD.2014.6974721},
doi = {10.1109/ICCD.2014.6974721},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/MaLZL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YaoC0MXY14,
author = {Song Yao and
Xiaoming Chen and
Yu Wang and
Yuchun Ma and
Yuan Xie and
Huazhong Yang},
title = {Efficient region-aware {P/G} {TSV} planning for 3D ICs},
booktitle = {Fifteenth International Symposium on Quality Electronic Design, {ISQED}
2014, Santa Clara, CA, USA, March 3-5, 2014},
pages = {171--178},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISQED.2014.6783321},
doi = {10.1109/ISQED.2014.6783321},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/YaoC0MXY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpt/2014,
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
publisher = {{IEEE}},
year = {2014},
url = {https://ieeexplore.ieee.org/xpl/conhome/7063887/proceeding},
isbn = {978-1-4799-6245-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/2014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/YuDMLWCG14,
author = {Bei Yu and
Sheqin Dong and
Yuchun Ma and
Tao Lin and
Yu Wang and
Song Chen and
Satoshi Goto},
title = {Network flow-based simultaneous retiming and slack budgeting for low
power design},
journal = {CoRR},
volume = {abs/1402.2460},
year = {2014},
url = {http://arxiv.org/abs/1402.2460},
eprinttype = {arXiv},
eprint = {1402.2460},
timestamp = {Thu, 04 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/YuDMLWCG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/ChenL0CXMY13,
author = {Xiaoming Chen and
Hong Luo and
Yu Wang and
Yu Cao and
Yuan Xie and
Yuchun Ma and
Huazhong Yang},
title = {Evaluation and mitigation of performance degradation under random
telegraph noise for digital circuits},
journal = {{IET} Circuits Devices Syst.},
volume = {7},
number = {5},
pages = {273--282},
year = {2013},
url = {https://doi.org/10.1049/iet-cds.2012.0361},
doi = {10.1049/IET-CDS.2012.0361},
timestamp = {Thu, 15 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/ChenL0CXMY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiMZCXH13,
author = {Zuowei Li and
Yuchun Ma and
Qiang Zhou and
Yici Cai and
Yuan Xie and
Tingting Huang},
title = {Thermal-aware {P/G} {TSV} planning for {IR} drop reduction in 3D ICs},
journal = {Integr.},
volume = {46},
number = {1},
pages = {1--9},
year = {2013},
url = {https://doi.org/10.1016/j.vlsi.2012.05.002},
doi = {10.1016/J.VLSI.2012.05.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiMZCXH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/HeLMWB13,
author = {Ruining He and
Guoqiang Liang and
Yuchun Ma and
Yu Wang and
Jinian Bian},
title = {Unification of {PR} Region floorplanning and Fine-Grained Placement
for Dynamic Partially Reconfigurable FPGAs},
journal = {J. Circuits Syst. Comput.},
volume = {22},
number = {4},
year = {2013},
url = {https://doi.org/10.1142/S0218126613500205},
doi = {10.1142/S0218126613500205},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/HeLMWB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/XuMLT13,
author = {Ning Xu and
Yuchun Ma and
Jia Liu and
Shou{-}Chun Tao},
title = {Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs},
journal = {J. Comput. Sci. Technol.},
volume = {28},
number = {4},
pages = {671--681},
year = {2013},
url = {https://doi.org/10.1007/s11390-013-1367-8},
doi = {10.1007/S11390-013-1367-8},
timestamp = {Mon, 20 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/XuMLT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiXMB13,
author = {Yuanyuan Li and
Ning Xu and
Yuchun Ma and
Jinian Bian},
title = {Incremental 3D NoC synthesis based on physical-aware router merging
algorithm},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811920},
doi = {10.1109/ASICON.2013.6811920},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiXMB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhangXMWB13,
author = {Jixin Zhang and
Ning Xu and
Yuchun Ma and
Yu Wang and
Jinian Bian},
title = {Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable
designs},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811919},
doi = {10.1109/ASICON.2013.6811919},
timestamp = {Wed, 14 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ZhangXMWB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/TaoCWMSWY13,
author = {Shuai Tao and
Xiaoming Chen and
Yu Wang and
Yuchun Ma and
Yiyu Shi and
Hui Wang and
Huazhong Yang},
title = {{HS3DPG:} Hierarchical simulation for 3D {P/G} network},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {509--514},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509647},
doi = {10.1109/ASPDAC.2013.6509647},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/TaoCWMSWY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscwd/YuanMBZ13,
author = {Zhongda Yuan and
Yuchun Ma and
Jinian Bian and
Kang Zhao},
editor = {Weiming Shen and
Weidong Li and
Jean{-}Paul A. Barth{\`{e}}s and
Junzhou Luo and
Haibin Zhu and
Jianming Yong and
Xiaoping Li},
title = {Automatic enhanced {CDFG} generation based on runtime instrumentation},
booktitle = {Proceedings of the 2013 {IEEE} 17th International Conference on Computer
Supported Cooperative Work in Design (CSCWD), Whistler, BC, Canada,
June 27-29, 2013},
pages = {92--97},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CSCWD.2013.6580945},
doi = {10.1109/CSCWD.2013.6580945},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/cscwd/YuanMBZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cscwd/LiangMZB13,
author = {Guoqiang Liang and
Yuchun Ma and
Kang Zhao and
Jinian Bian},
editor = {Weiming Shen and
Weidong Li and
Jean{-}Paul A. Barth{\`{e}}s and
Junzhou Luo and
Haibin Zhu and
Jianming Yong and
Xiaoping Li},
title = {Efficient custom instruction generation based on characterizing of
basic blocks},
booktitle = {Proceedings of the 2013 {IEEE} 17th International Conference on Computer
Supported Cooperative Work in Design (CSCWD), Whistler, BC, Canada,
June 27-29, 2013},
pages = {98--103},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CSCWD.2013.6580946},
doi = {10.1109/CSCWD.2013.6580946},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cscwd/LiangMZB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuDWMXQY13,
author = {Wulong Liu and
Haixiao Du and
Yu Wang and
Yuchun Ma and
Yuan Xie and
Jinguo Quan and
Huazhong Yang},
title = {TSV-aware topology generation for 3D Clock Tree Synthesis},
booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013,
Santa Clara, CA, USA, March 4-6, 2013},
pages = {300--307},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISQED.2013.6523626},
doi = {10.1109/ISQED.2013.6523626},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LiuDWMXQY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiLDWMY13,
author = {Xin Li and
Wulong Liu and
Haixiao Du and
Yu Wang and
Yuchun Ma and
Huazhong Yang},
title = {Whitespace-aware {TSV} arrangement in 3D clock tree synthesis},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2013, Natal,
Brazil, August 5-7, 2013},
pages = {115--120},
publisher = {{IEEE} Computer Socity},
year = {2013},
url = {https://doi.org/10.1109/ISVLSI.2013.6654632},
doi = {10.1109/ISVLSI.2013.6654632},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiLDWMY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/LiuM0LB13,
author = {Qingyu Liu and
Yuchun Ma and
Yu Wang and
Wayne Luk and
Jinian Bian},
title = {{RALP:} Reconvergence-aware layer partitioning for 3D FPGAs},
booktitle = {2012 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2013, Cancun, Mexico, December 9-11, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ReConFig.2013.6732327},
doi = {10.1109/RECONFIG.2013.6732327},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/LiuM0LB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenWCMY12,
author = {Xiaoming Chen and
Yu Wang and
Yu Cao and
Yuchun Ma and
Huazhong Yang},
title = {Variation-Aware Supply Voltage Assignment for Simultaneous Power and
Aging Optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {11},
pages = {2143--2147},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2168433},
doi = {10.1109/TVLSI.2011.2168433},
timestamp = {Thu, 15 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenWCMY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/HeLMWB12,
author = {Ruining He and
Guoqiang Liang and
Yuchun Ma and
Yu Wang and
Jinian Bian},
editor = {Oliver C. S. Choy and
Ray C. C. Cheung and
Peter M. Athanas and
Kentaro Sano},
title = {{PDPR:} Fine-Grained Placement for Dynamic Partially Reconfigurable
FPGAs},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications -
8th International Symposium, {ARC} 2012, Hong Kong, China, March 19-23,
2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7199},
pages = {350--356},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-28365-9\_31},
doi = {10.1007/978-3-642-28365-9\_31},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/HeLMWB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiMZCWHX12,
author = {Zuowei Li and
Yuchun Ma and
Qiang Zhou and
Yici Cai and
Yu Wang and
Tingting Huang and
Yuan Xie},
title = {Thermal-aware power network design for {IR} drop reduction in 3D ICs},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {47--52},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164995},
doi = {10.1109/ASPDAC.2012.6164995},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiMZCWHX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HeMZB12,
author = {Ruining He and
Yuchun Ma and
Kang Zhao and
Jinian Bian},
editor = {Alan J. Hu},
title = {{ISBA:} An independent set-based algorithm for automated partial reconfiguration
module generation},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {500--507},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429491},
doi = {10.1145/2429384.2429491},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HeMZB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/YuanMB12,
author = {Zhongda Yuan and
Yuchun Ma and
Jinian Bian},
title = {{SMPP:} Generic {SAT} Solver over Reconfigurable Hardware Accelerator},
booktitle = {26th {IEEE} International Parallel and Distributed Processing Symposium
Workshops {\&} PhD Forum, {IPDPS} 2012, Shanghai, China, May 21-25,
2012},
pages = {443--448},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/IPDPSW.2012.57},
doi = {10.1109/IPDPSW.2012.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/YuanMB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/WangDMGC12,
author = {Kan Wang and
Sheqin Dong and
Yuchun Ma and
Satoshi Goto and
Jason Cong},
editor = {Keith A. Bowman and
Kamesh V. Gadepally and
Pallab Chatterjee and
Mark M. Budnik and
Lalitha Immaneni},
title = {Leakage-aware performance-driven TSV-planning based on network flow
algorithm in 3D ICs},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
2012, Santa Clara, CA, USA, March 19-21, 2012},
pages = {129--136},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISQED.2012.6187485},
doi = {10.1109/ISQED.2012.6187485},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/WangDMGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LuoWCXMY12,
author = {Hong Luo and
Yu Wang and
Yu Cao and
Yuan Xie and
Yuchun Ma and
Huazhong Yang},
title = {Temporal Performance Degradation under {RTN:} Evaluation and Mitigation
for Nanoscale Circuits},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {183--188},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.35},
doi = {10.1109/ISVLSI.2012.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LuoWCXMY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WangDMWHC11,
author = {Kan Wang and
Sheqin Dong and
Yuchun Ma and
Yu Wang and
Xianlong Hong and
Jason Cong},
title = {Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence
in 3D ICs},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {94-A},
number = {12},
pages = {2490--2498},
year = {2011},
url = {https://doi.org/10.1587/transfun.E94.A.2490},
doi = {10.1587/TRANSFUN.E94.A.2490},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WangDMWHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiuMXW11,
author = {Jia Liu and
Yuchun Ma and
Ning Xu and
Yu Wang},
title = {Incremental layout optimization for NoC designs based on {MILP} formulation},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {357--360},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157195},
doi = {10.1109/ASICON.2011.6157195},
timestamp = {Wed, 14 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asicon/LiuMXW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuWLMXY11,
author = {Wulong Liu and
Yu Wang and
Wei Liu and
Yuchun Ma and
Yuan Xie and
Huazhong Yang},
title = {On-chip hybrid power supply system for wireless sensor nodes},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {43--48},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722229},
doi = {10.1109/ASPDAC.2011.5722229},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiuWLMXY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangMDWHC11,
author = {Kan Wang and
Yuchun Ma and
Sheqin Dong and
Yu Wang and
Xianlong Hong and
Jason Cong},
title = {Rethinking thermal via planning with timing-power-temperature dependence
for 3D ICs},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {261--266},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722195},
doi = {10.1109/ASPDAC.2011.5722195},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WangMDWHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YuDMLWCG11,
author = {Bei Yu and
Sheqin Dong and
Yuchun Ma and
Tao Lin and
Yu Wang and
Song Chen and
Satoshi Goto},
title = {Network flow-based simultaneous retiming and slack budgeting for low
power design},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {473--478},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722236},
doi = {10.1109/ASPDAC.2011.5722236},
timestamp = {Thu, 04 Apr 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YuDMLWCG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/SongZMXW11,
author = {Binjie Song and
Shan Zeng and
Yuchun Ma and
Ning Xu and
Yu Wang},
title = {Tree-Based Partitioning Approach for Network-on-Chip Synthesis},
booktitle = {12th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2011, Jinan, China, September 15-17, 2011},
pages = {465--470},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/CAD/Graphics.2011.20},
doi = {10.1109/CAD/GRAPHICS.2011.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cadgraphics/SongZMXW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LuoCVWCCMY11,
author = {Hong Luo and
Xiaoming Chen and
Jyothi Velamala and
Yu Wang and
Yu Cao and
Vikas Chandra and
Yuchun Ma and
Huazhong Yang},
title = {Circuit-level delay modeling considering both {TDDB} and {NBTI}},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {14--21},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770697},
doi = {10.1109/ISQED.2011.5770697},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LuoCVWCCMY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LinDCMHG11,
author = {Tao Lin and
Sheqin Dong and
Song Chen and
Yuchun Ma and
Ou He and
Satoshi Goto},
title = {Novel and efficient min cut based voltage assignment in gate level},
booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
pages = {150--155},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISQED.2011.5770719},
doi = {10.1109/ISQED.2011.5770719},
timestamp = {Thu, 30 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/LinDCMHG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HeDM10,
author = {Xu He and
Sheqin Dong and
Yuchun Ma},
title = {Signal through-the-silicon via planning and pin assignment for thermal
and wire length optimization in 3D ICs},
journal = {Integr.},
volume = {43},
number = {4},
pages = {342--352},
year = {2010},
url = {https://doi.org/10.1016/j.vlsi.2010.06.001},
doi = {10.1016/J.VLSI.2010.06.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/HeDM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/MaZZH10,
author = {Yuchun Ma and
Qiang Zhou and
Pingqiang Zhou and
Xianlong Hong},
title = {Thermal Impacts of Leakage Power in 2D/3D floorplanning},
journal = {J. Circuits Syst. Comput.},
volume = {19},
number = {7},
pages = {1483--1495},
year = {2010},
url = {https://doi.org/10.1142/S0218126610006773},
doi = {10.1142/S0218126610006773},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/MaZZH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuMHW10,
author = {Shenghua Liu and
Yuchun Ma and
Xianlong Hong and
Yu Wang},
title = {Simultaneous slack budgeting and retiming for synchronous circuits
optimization},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {49--54},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419919},
doi = {10.1109/ASPDAC.2010.5419919},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiuMHW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiMXWH10,
author = {Li Li and
Yuchun Ma and
Ning Xu and
Yu Wang and
Xianlong Hong},
title = {{PS-FPG:} pattern selection based co-design of floorplan and power/ground
network with wiring resource optimization},
booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
pages = {769--774},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ASPDAC.2010.5419785},
doi = {10.1109/ASPDAC.2010.5419785},
timestamp = {Fri, 13 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LiMXWH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/MaLWH09,
author = {Yuchun Ma and
Xin Li and
Yu Wang and
Xianlong Hong},
title = {Thermal-Aware Incremental Floorplanning for 3D ICs Based on {MILP}
Formulation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {92-A},
number = {12},
pages = {2979--2989},
year = {2009},
url = {https://doi.org/10.1587/transfun.E92.A.2979},
doi = {10.1587/TRANSFUN.E92.A.2979},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/MaLWH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiMH09,
author = {Xin Li and
Yuchun Ma and
Xianlong Hong},
editor = {Kazutoshi Wakabayashi},
title = {A novel thermal optimization flow using incremental floorplanning
for 3D ICs},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {347--352},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796505},
doi = {10.1109/ASPDAC.2009.4796505},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiMH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fskd/MaoMXHW09,
author = {Fubing Mao and
Yuchun Ma and
Ning Xu and
Xianlong Hong and
Yu Wang},
editor = {Yixin Chen and
Hepu Deng and
Degan Zhang and
Yingyuan Xiao},
title = {Multi-objective Floorplanning Based on Fuzzy Logic},
booktitle = {Sixth International Conference on Fuzzy Systems and Knowledge Discovery,
{FSKD} 2009, Tianjin, China, 14-16 August 2009, 6 Volumes},
pages = {331--335},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FSKD.2009.490},
doi = {10.1109/FSKD.2009.490},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fskd/MaoMXHW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChenWCMY09,
author = {Xiaoming Chen and
Yu Wang and
Yu Cao and
Yuchun Ma and
Huazhong Yang},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {Variation-aware supply voltage assignment for minimizing circuit degradation
and leakage},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {39--44},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594244},
doi = {10.1145/1594233.1594244},
timestamp = {Thu, 15 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ChenWCMY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/MaQHH09,
author = {Yuchun Ma and
Xiang Qiu and
Xiangqing He and
Xianlong Hong},
title = {Incremental power optimization for multiple supply voltage design},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {280--286},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810308},
doi = {10.1109/ISQED.2009.4810308},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/MaQHH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/HeDMH09,
author = {Xu He and
Sheqin Dong and
Yuchun Ma and
Xianlong Hong},
title = {Simultaneous buffer and interlayer via planning for 3D floorplanning},
booktitle = {10th International Symposium on Quality of Electronic Design {(ISQED}
2009), 16-18 March 2009, San Jose, CA, {USA}},
pages = {740--745},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISQED.2009.4810385},
doi = {10.1109/ISQED.2009.4810385},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/HeDMH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiMXWH09,
author = {Li Li and
Yuchun Ma and
Ning Xu and
Yu Wang and
Xianlong Hong},
title = {Modern Floorplanning with Boundary Clustering Constraint},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {79--84},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.24},
doi = {10.1109/ISVLSI.2009.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiMXWH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/MaLKRC08,
author = {Yuchun Ma and
Yongxiang Liu and
Eren Kursun and
Glenn Reinman and
Jason Cong},
title = {Investigating the effects of fine-grain three-dimensional integration
on microarchitecture design},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {4},
number = {4},
pages = {17:1--17:30},
year = {2008},
url = {https://doi.org/10.1145/1412587.1412590},
doi = {10.1145/1412587.1412590},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/MaLKRC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiMHDC08,
author = {Xin Li and
Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Jason Cong},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {{LP} based white space redistribution for thermal via planning and
performance optimization in 3D ICs},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {209--212},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4483942},
doi = {10.1109/ASPDAC.2008.4483942},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiMHDC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fskd/LiuMG08,
author = {Jiemin Liu and
Yuchun Ma and
Yuan Gao},
editor = {Jun Ma and
Yilong Yin and
Jian Yu and
Shuigeng Zhou},
title = {{MRAPF:} Minimum {RTT} Asymmetric-Path First for Mobile Multi-homed
End-to-End Transfer},
booktitle = {Fifth International Conference on Fuzzy Systems and Knowledge Discovery,
{FSKD} 2008, 18-20 October 2008, Jinan, Shandong, China, Proceedings,
Volume 4},
pages = {86--90},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/FSKD.2008.193},
doi = {10.1109/FSKD.2008.193},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fskd/LiuMG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/QiuMHH08,
author = {Xiang Qiu and
Yuchun Ma and
Xiangqing He and
Xianlong Hong},
title = {{IPOSA:} {A} Novel Slack Distribution Algorithm for Interconnect Power
Optimization},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {873--876},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479853},
doi = {10.1109/ISQED.2008.4479853},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/QiuMHH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuDMLH07,
author = {Jiayi Liu and
Sheqin Dong and
Yuchun Ma and
Di Long and
Xianlong Hong},
title = {Thermal-driven Symmetry Constraint for Analog Layout with {CBL} Representation},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {191--196},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357984},
doi = {10.1109/ASPDAC.2007.357984},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LiuDMLH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MaLCHRDZ07,
author = {Yuchun Ma and
Zhuoyuan Li and
Jason Cong and
Xianlong Hong and
Glenn Reinman and
Sheqin Dong and
Qiang Zhou},
title = {Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {920--925},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358107},
doi = {10.1109/ASPDAC.2007.358107},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MaLCHRDZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cadgraphics/ZhouMZH07,
author = {Pingqiang Zhou and
Yuchun Ma and
Qiang Zhou and
Xianlong Hong},
title = {Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning},
booktitle = {10th International Conference on Computer-Aided Design and Computer
Graphics, CAD/Graphics 2007, Beijing, China, 15-18 October, 2007},
pages = {338--343},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/CADCG.2007.4407905},
doi = {10.1109/CADCG.2007.4407905},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/cadgraphics/ZhouMZH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/HeDBMH07,
author = {Ou He and
Sheqin Dong and
Jinian Bian and
Yuchun Ma and
Xianlong Hong},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {An effective buffer planning algorithm for {IP} based fixed-outline
{SOC} placement},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {564--569},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228917},
doi = {10.1145/1228784.1228917},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/HeDBMH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhouMLDSZHZ07,
author = {Pingqiang Zhou and
Yuchun Ma and
Zhuoyuan Li and
Robert P. Dick and
Li Shang and
Hai Zhou and
Xianlong Hong and
Qiang Zhou},
editor = {Georges G. E. Gielen},
title = {3D-STAF: scalable temperature and leakage aware floorplanning for
three-dimensional integrated circuits},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {590--597},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397329},
doi = {10.1109/ICCAD.2007.4397329},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ZhouMLDSZHZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LiuMKRC07,
author = {Yongxiang Liu and
Yuchun Ma and
Eren Kursun and
Glenn Reinman and
Jason Cong},
title = {Fine grain 3D integration for microarchitecture design through cube
packing exploration},
booktitle = {25th International Conference on Computer Design, {ICCD} 2007, 7-10
October 2007, Lake Tahoe, CA, USA, Proceedings},
pages = {259--266},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ICCD.2007.4601911},
doi = {10.1109/ICCD.2007.4601911},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LiuMKRC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangDHM07,
author = {Lingyi Zhang and
Sheqin Dong and
Xianlong Hong and
Yuchun Ma},
title = {A Fast 3D-BSG Algorithm for 3D Packing Problem},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {2044--2047},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378499},
doi = {10.1109/ISCAS.2007.378499},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ZhangDHM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YangDMH07,
author = {Liu Yang and
Sheqin Dong and
Yuchun Ma and
Xianlong Hong},
title = {Interconnect Power Optimization Based on Timing Analysis},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {119--124},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.61},
doi = {10.1109/ISVLSI.2007.61},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YangDMH07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/WeiDHM07,
author = {Yaoguang Wei and
Sheqin Dong and
Xianlong Hong and
Yuchun Ma},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {An accurate and efficient probabilistic congestion estimation model
in x architecture},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {25--32},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231962},
doi = {10.1145/1231956.1231962},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/WeiDHM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/MaHDCG06,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Chung{-}Kuan Cheng and
Jun Gu},
title = {General Floorplans with L/T-Shaped Blocks Using Corner Block List},
journal = {J. Comput. Sci. Technol.},
volume = {21},
number = {6},
pages = {922--926},
year = {2006},
url = {https://doi.org/10.1007/s11390-006-0922-y},
doi = {10.1007/S11390-006-0922-Y},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/MaHDCG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChenDHMC06,
author = {Song Chen and
Sheqin Dong and
Xianlong Hong and
Yuchun Ma and
Chung{-}Kuan Cheng},
title = {{VLSI} Block Placement With Alignment Constraints},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {8},
pages = {622--626},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.876374},
doi = {10.1109/TCSII.2006.876374},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChenDHMC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/YangDHM06,
author = {Liu Yang and
Sheqin Dong and
Xianlong Hong and
Yuchun Ma},
title = {A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {792--795},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342140},
doi = {10.1109/APCCAS.2006.342140},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/YangDHM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/CongJMRWZ06,
author = {Jason Cong and
Ashok Jagannathan and
Yuchun Ma and
Glenn Reinman and
Jie Wei and
Yan Zhang},
editor = {Fumiyasu Hirose},
title = {An automated design flow for 3D microarchitecture evaluation},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {384--389},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594713},
doi = {10.1109/ASPDAC.2006.1594713},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/CongJMRWZ06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaHDCCG05,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Buffer planning as an Integral part of floorplanning with consideration
of routing congestion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {24},
number = {4},
pages = {609--621},
year = {2005},
url = {https://doi.org/10.1109/TCAD.2005.844103},
doi = {10.1109/TCAD.2005.844103},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaHDCCG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MaHDCC05,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Chung{-}Kuan Cheng},
title = {Performance constrained floorplanning based on partial clustering
{[IC} layout]},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {1863--1866},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464974},
doi = {10.1109/ISCAS.2005.1464974},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MaHDCC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenHDMC05,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Chung{-}Kuan Cheng},
title = {{VLSI} block placement with alignment constraints based on corner
block list},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {6222--6225},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1466062},
doi = {10.1109/ISCAS.2005.1466062},
timestamp = {Thu, 30 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenHDMC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/MaHDCC05,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Chung{-}Kuan Cheng},
title = {Buffer Planning Algorithm Based on Partial Clustered Floorplanning},
booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED}
2005), 21-23 March 2005, San Jose, CA, {USA}},
pages = {213--219},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISQED.2005.27},
doi = {10.1109/ISQED.2005.27},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/MaHDCC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenHDMC05,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Chung{-}Kuan Cheng},
title = {Floorplanning with Consideration of White Space Resource Distribution
for Repeater Planning},
booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED}
2005), 21-23 March 2005, San Jose, CA, {USA}},
pages = {628--633},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISQED.2005.58},
doi = {10.1109/ISQED.2005.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/ChenHDMC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/HongMDCCG04,
author = {Xianlong Hong and
Yuchun Ma and
Sheqin Dong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Corner block list representation and its application with boundary
constraints},
journal = {Sci. China Ser. {F} Inf. Sci.},
volume = {47},
number = {1},
pages = {1--19},
year = {2004},
url = {https://doi.org/10.1360/01yf0558},
doi = {10.1360/01YF0558},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/HongMDCCG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/ChenHDMCCJ04,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {A buffer planning algorithm for chip-level floorplanning},
journal = {Sci. China Ser. {F} Inf. Sci.},
volume = {47},
number = {6},
pages = {763--776},
year = {2004},
url = {https://doi.org/10.1360/03yf0028},
doi = {10.1360/03YF0028},
timestamp = {Mon, 18 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/ChenHDMCCJ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcst/ChenHDMCG04,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Fast Evaluation of Bounded Slice-Line Grid},
journal = {J. Comput. Sci. Technol.},
volume = {19},
number = {6},
pages = {973--980},
year = {2004},
url = {https://doi.org/10.1007/BF02973462},
doi = {10.1007/BF02973462},
timestamp = {Thu, 30 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcst/ChenHDMCG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MaHDCCG04,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Stairway compaction using corner block list and its applications with
rectilinear blocks},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {9},
number = {2},
pages = {199--211},
year = {2004},
url = {https://doi.org/10.1145/989995.989998},
doi = {10.1145/989995.989998},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MaHDCCG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenHDMCCG04,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
editor = {Masaharu Imai},
title = {A buffer planning algorithm with congestion optimization},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {615--620},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.6},
doi = {10.1109/ASPDAC.2004.6},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChenHDMCCG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MaHDCCCG04,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
editor = {Masaharu Imai},
title = {Buffer allocation algorithm with consideration of routing congestion},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {621--623},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.66},
doi = {10.1109/ASPDAC.2004.66},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/MaHDCCCG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChenHDMCCG03,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
editor = {Hiroto Yasuura},
title = {A buffer planning algorithm based on dead space redistribution},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {435--438},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119859},
doi = {10.1145/1119772.1119859},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChenHDMCCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaHDCCCG03,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Dynamic global buffer planning optimization based on detail block
locating and congestion analysis},
booktitle = {Proceedings of the 40th Design Automation Conference, {DAC} 2003,
Anaheim, CA, USA, June 2-6, 2003},
pages = {806--811},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/775832.776036},
doi = {10.1145/775832.776036},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MaHDCCCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MaHDCCCG03,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Yici Cai and
Song Chen and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Arbitrary convex and concave rectilinear block packing based on corner
block list},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {493--496},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206328},
doi = {10.1109/ISCAS.2003.1206328},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MaHDCCCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenHDMCCG03,
author = {Song Chen and
Xianlong Hong and
Sheqin Dong and
Yuchun Ma and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Evaluating a bounded slice-line grid assignment in O(nlogn) time},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {708--711},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206227},
doi = {10.1109/ISCAS.2003.1206227},
timestamp = {Thu, 30 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenHDMCCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/MaHDCCCG03,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Song Chen and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
editor = {Massoud Pedram and
Charles J. Alpert},
title = {An integrated floorplanning with an efficient buffer planning algorithm},
booktitle = {Proceedings of the 2003 International Symposium on Physical Design,
{ISPD} 2003, Monterey, CA, USA, April 6-9, 2003},
pages = {136--142},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/640000.640031},
doi = {10.1145/640000.640031},
timestamp = {Tue, 06 Nov 2018 11:07:46 +0100},
biburl = {https://dblp.org/rec/conf/ispd/MaHDCCCG03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MaHDCCG02,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Stairway Compaction using Corner Block List and Its Applications with
Rectilinear Blocks},
booktitle = {Proceedings of the 7th Asia and South Pacific Design Automation Conference
{(ASP-DAC} 2002), and the 15th International Conference on {VLSI}
Design {(VLSI} Design 2002), Bangalore, India, January 7-11, 2002},
pages = {387--392},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ASPDAC.2002.994952},
doi = {10.1109/ASPDAC.2002.994952},
timestamp = {Mon, 14 Nov 2022 15:28:09 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MaHDCCG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MaHDCCG01,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Floorplanning with abutment constraints based on corner block list},
journal = {Integr.},
volume = {31},
number = {1},
pages = {65--77},
year = {2001},
url = {https://doi.org/10.1016/S0167-9260(01)00022-0},
doi = {10.1016/S0167-9260(01)00022-0},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MaHDCCG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MaDHCCG01,
author = {Yuchun Ma and
Sheqin Dong and
Xianlong Hong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
editor = {Satoshi Goto},
title = {{VLSI} floorplanning with boundary constraints based on corner block
list},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {509--514},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370521},
doi = {10.1145/370155.370521},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MaDHCCG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/MaHDCCG01,
author = {Yuchun Ma and
Xianlong Hong and
Sheqin Dong and
Yici Cai and
Chung{-}Kuan Cheng and
Jun Gu},
title = {Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks
based on Corner Block List},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {770--775},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.379063},
doi = {10.1145/378239.379063},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/MaHDCCG01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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