BibTeX records: Chi Lan Phuong Nguyen

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@article{DBLP:journals/ieicet/MochizukiMMNSIM17,
  author       = {Seiji Mochizuki and
                  Katsushige Matsubara and
                  Keisuke Matsumoto and
                  Chi Lan Phuong Nguyen and
                  Tetsuya Shibayama and
                  Kenichi Iwata and
                  Katsuya Mizumoto and
                  Takahiro Irita and
                  Hirotaka Hara and
                  Toshihiro Hattori},
  title        = {A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm
                  {CMOS} for In-Vehicle Information Systems},
  journal      = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
  volume       = {100-A},
  number       = {12},
  pages        = {2878--2887},
  year         = {2017},
  url          = {https://doi.org/10.1587/transfun.E100.A.2878},
  doi          = {10.1587/TRANSFUN.E100.A.2878},
  timestamp    = {Sat, 11 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ieicet/MochizukiMMNSIM17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icicdt/NguyenNCMMMI16,
  author       = {Chi Lan Phuong Nguyen and
                  My Phi Ngoc Nguyen and
                  Hung Van Cao and
                  Katsushige Matsubara and
                  Keisuke Matsumoto and
                  Seiji Mochizuki and
                  Kenichi Iwata},
  title        = {71{\%} Reducing the memory bandwidth requirement for a multi-standard
                  video codec by lossless compression of video using a combination of
                  2D-DPCM and Variable Length Coding},
  booktitle    = {International Conference on {IC} Design and Technology, {ICICDT} 2016,
                  Ho Chi Minh, Vietnam, June 27-29, 2016},
  pages        = {1--5},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ICICDT.2016.7542036},
  doi          = {10.1109/ICICDT.2016.7542036},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/icicdt/NguyenNCMMMI16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/MochizukiMMNSIM16,
  author       = {Seiji Mochizuki and
                  Katsushige Matsubara and
                  Keisuke Matsumoto and
                  Chi Lan Phuong Nguyen and
                  Tetsuya Shibayama and
                  Kenichi Iwata and
                  Katsuya Mizumoto and
                  Takahiro Irita and
                  Hirotaka Hara and
                  Toshihiro Hattori},
  title        = {4.4 {A} 197mW 70ms-latency full-HD 12-channel video-processing SoC
                  for car information systems},
  booktitle    = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2016, San Francisco, CA, USA, January 31 - February 4, 2016},
  pages        = {78--79},
  publisher    = {{IEEE}},
  year         = {2016},
  url          = {https://doi.org/10.1109/ISSCC.2016.7417915},
  doi          = {10.1109/ISSCC.2016.7417915},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/MochizukiMMNSIM16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}