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ORCIDBibTeX records: Xin Si
@article{DBLP:journals/tcasII/ChenZXS24,
author = {Jinwu Chen and
Yitong Zhao and
Tianzhu Xiong and
Xin Si},
title = {An {INT8} Charge-Digital Hybrid Compute-In-Memory Macro With CNN-Friendly
Shift-Feed Register Design},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {71},
number = {3},
pages = {1371--1375},
year = {2024},
url = {https://doi.org/10.1109/TCSII.2023.3323211},
doi = {10.1109/TCSII.2023.3323211},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasII/ChenZXS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShanZLDCQGYS24,
author = {Weiwei Shan and
Kaize Zhou and
Keran Li and
Yuxuan Du and
Zhuo Chen and
Junyi Qian and
Haitao Ge and
Jun Yang and
Xin Si},
title = {14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative
Control Based on Current and Voltage Prediction Applied to a Multicore
Processor in 28nm {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {256--258},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454398},
doi = {10.1109/ISSCC49657.2024.10454398},
timestamp = {Tue, 19 Mar 2024 09:04:31 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ShanZLDCQGYS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoCDCYHZZTZCYZRXWLSLCSYS24,
author = {An Guo and
Xi Chen and
Fangyuan Dong and
Jinwu Chen and
Zhihang Yuan and
Xing Hu and
Yuanpeng Zhang and
Jingmin Zhang and
Yuchen Tang and
Zhican Zhang and
Gang Chen and
Dawei Yang and
Zhaoyang Zhang and
Lizheng Ren and
Tianzhu Xiong and
Bo Wang and
Bo Liu and
Weiwei Shan and
Xinning Liu and
Hao Cai and
Guangyu Sun and
Jun Yang and
Xin Si},
title = {34.3 {A} 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro
with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer
and CNNs},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
San Francisco, CA, USA, February 18-22, 2024},
pages = {570--572},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454278},
doi = {10.1109/ISSCC49657.2024.10454278},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoCDCYHZZTZCYZRXWLSLCSYS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/chinaf/ZhangCCGWXKPHSY23,
author = {Zhaoyang Zhang and
Jinwu Chen and
Xi Chen and
An Guo and
Bo Wang and
Tianzhu Xiong and
Yuyao Kong and
Xingyu Pu and
Shengnan He and
Xin Si and
Jun Yang},
title = {From macro to microarchitecture: reviews and trends of SRAM-based
compute-in-memory circuits},
journal = {Sci. China Inf. Sci.},
volume = {66},
number = {10},
year = {2023},
url = {https://doi.org/10.1007/s11432-023-3800-9},
doi = {10.1007/S11432-023-3800-9},
timestamp = {Fri, 06 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/chinaf/ZhangCCGWXKPHSY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/GuoYSLHTWSLCLWY23,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Hao Li and
Te Hu and
Limei Tang and
Yabing Wang and
Hao Sun and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {TT@CIM: {A} Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity
Optimization and Variable Precision Quantization},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {3},
pages = {852--866},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3198413},
doi = {10.1109/JSSC.2022.3198413},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/GuoYSLHTWSLCLWY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23,
author = {Jian{-}Wei Su and
Yen{-}Chi Chou and
Ruhui Liu and
Ta{-}Wei Liu and
Pei{-}Jung Lu and
Ping{-}Chun Wu and
Yen{-}Lin Chung and
Li{-}Yang Hong and
Jin{-}Sheng Ren and
Tianlong Pan and
Chuan{-}Jia Jhang and
Wei{-}Hsing Huang and
Chih{-}Han Chien and
Peng{-}I Mei and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Shih{-}Chieh Chang and
Wei{-}Chung Lo and
Chih{-}I Wu and
Xin Si and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 8-b-Precision 6T {SRAM} Computing-in-Memory Macro Using Segmented-Bitline
Charge-Sharing Scheme for {AI} Edge Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {58},
number = {3},
pages = {877--892},
year = {2023},
url = {https://doi.org/10.1109/JSSC.2022.3199077},
doi = {10.1109/JSSC.2022.3199077},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SuCLLLWCHRPJHCMLSCLWSLLHTC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/KongCSY23,
author = {Yuyao Kong and
Xi Chen and
Xin Si and
Jun Yang},
title = {Evaluation Platform of Time-Domain Computing-in-Memory Circuits},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {70},
number = {3},
pages = {1174--1178},
year = {2023},
url = {https://doi.org/10.1109/TCSII.2022.3229437},
doi = {10.1109/TCSII.2022.3229437},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/KongCSY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoSCDPLZRXDGZZKXWCSY23,
author = {An Guo and
Xin Si and
Xi Chen and
Fangyuan Dong and
Xingyu Pu and
Dongqi Li and
Yongliang Zhou and
Lizheng Ren and
Yeyang Xue and
Xueshan Dong and
Hui Gao and
Yiran Zhang and
Jingmin Zhang and
Yuyao Kong and
Tianzhu Xiong and
Bo Wang and
Hao Cai and
Weiwei Shan and
Jun Yang},
title = {A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit
and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point
CNNs},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {128--129},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067260},
doi = {10.1109/ISSCC42615.2023.10067260},
timestamp = {Sun, 30 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/GuoSCDPLZRXDGZZKXWCSY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/WangXFZLRLYXXHKZGSY23,
author = {Bo Wang and
Chen Xue and
Zhongyuan Feng and
Zhaoyang Zhang and
Han Liu and
Lizheng Ren and
Xiang Li and
Anran Yin and
Tianzhu Xiong and
Yeyang Xue and
Shengnan He and
Yuyao Kong and
Yongliang Zhou and
An Guo and
Xin Si and
Jun Yang},
title = {A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL
6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {134--135},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067526},
doi = {10.1109/ISSCC42615.2023.10067526},
timestamp = {Wed, 29 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/WangXFZLRLYXXHKZGSY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/CaiBHZCGTLSWYS23,
author = {Hao Cai and
Zhong{-}Jian Bian and
Yaoru Hou and
Yongliang Zhou and
Jia{-}Le Cui and
Yanan Guo and
Xiaoyun Tian and
Bo Liu and
Xin Si and
Zhen Wang and
Jun Yang and
Weiwei Shan},
title = {A 28nm 2Mb {STT-MRAM} Computing-in-Memory Macro with a Refined Bit-Cell
and 22.4 - 41.5TOPS/W for {AI} Inference},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2023,
San Francisco, CA, USA, February 19-23, 2023},
pages = {500--501},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISSCC42615.2023.10067339},
doi = {10.1109/ISSCC42615.2023.10067339},
timestamp = {Thu, 11 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/CaiBHZCGTLSWYS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/ZhangWCCS23,
author = {Yiran Zhang and
Bo Wang and
Jinwu Chen and
Xi Chen and
Xin Si},
title = {Evaluation Model for Current-Domain SRAM-based Computing-in-Memory
Circuits},
booktitle = {16th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023},
pages = {160--165},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/MCSoC60832.2023.00032},
doi = {10.1109/MCSOC60832.2023.00032},
timestamp = {Fri, 09 Feb 2024 20:38:48 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/ZhangWCCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ccfthpc/GuoXCS22,
author = {An Guo and
Chen Xue and
Xi Chen and
Xin Si},
title = {{VCCIM:} a voltage coupling based computing-in-memory architecture
in 28 nm for edge {AI} applications},
journal = {{CCF} Trans. High Perform. Comput.},
volume = {4},
number = {4},
pages = {407--420},
year = {2022},
url = {https://doi.org/10.1007/s42514-022-00111-1},
doi = {10.1007/S42514-022-00111-1},
timestamp = {Mon, 13 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ccfthpc/GuoXCS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SuSCCHTLLLWCRCW22,
author = {Jian{-}Wei Su and
Xin Si and
Yen{-}Chi Chou and
Ting{-}Wei Chang and
Wei{-}Hsing Huang and
Yung{-}Ning Tu and
Ruhui Liu and
Pei{-}Jung Lu and
Ta{-}Wei Liu and
Jing{-}Hong Wang and
Yen{-}Lin Chung and
Jin{-}Sheng Ren and
Fu{-}Chun Chang and
Yuan Wu and
Hongwu Jiang and
Shanshi Huang and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Chih{-}I Wu and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shimeng Yu and
Meng{-}Fan Chang},
title = {Two-Way Transpose Multibit 6T {SRAM} Computing-in-Memory Macro for
Inference-Training {AI} Edge Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {2},
pages = {609--624},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2021.3108344},
doi = {10.1109/JSSC.2021.3108344},
timestamp = {Tue, 20 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/SuSCCHTLLLWCRCW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/YueLYFHSZSLWCDL22,
author = {Jinshan Yue and
Yongpan Liu and
Zhe Yuan and
Xiaoyu Feng and
Yifan He and
Wenyu Sun and
Zhixiao Zhang and
Xin Si and
Ruhui Liu and
Zi Wang and
Meng{-}Fan Chang and
Chunmeng Dou and
Xueqing Li and
Ming Liu and
Huazhong Yang},
title = {{STICKER-IM:} {A} 65 nm Computing-in-Memory {NN} Processor Using Block-Wise
Sparsity Optimization and Inter/Intra-Macro Data Reuse},
journal = {{IEEE} J. Solid State Circuits},
volume = {57},
number = {8},
pages = {2560--2573},
year = {2022},
url = {https://doi.org/10.1109/JSSC.2022.3148273},
doi = {10.1109/JSSC.2022.3148273},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/YueLYFHSZSLWCDL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChenGXSY22,
author = {Xi Chen and
An Guo and
Xinbing Xu and
Xin Si and
Jun Yang},
title = {A Quantization Model Based on a Floating-point Computing-in-Memory
Architecture},
booktitle = {{IEEE} Asia Pacific Conference on Circuit and Systems, {APCCAS} 2022,
Shenzhen, China, November 11-13, 2022},
pages = {493--496},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/APCCAS55924.2022.10090283},
doi = {10.1109/APCCAS55924.2022.10090283},
timestamp = {Sat, 22 Apr 2023 16:25:51 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ChenGXSY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/FengWZGS22,
author = {Zhongyuan Feng and
Bo Wang and
Zhaoyang Zhang and
An Guo and
Xin Si},
title = {A Booth-based Digital Compute-in-Memory Marco for Processing Transformer
Model},
booktitle = {{IEEE} Asia Pacific Conference on Circuit and Systems, {APCCAS} 2022,
Shenzhen, China, November 11-13, 2022},
pages = {524--527},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/APCCAS55924.2022.10090256},
doi = {10.1109/APCCAS55924.2022.10090256},
timestamp = {Sat, 22 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/FengWZGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/LiWSZYWHNZLZCGS22,
author = {Xingchen Li and
Bingzhe Wu and
Guangyu Sun and
Zhe Zhang and
Zhihang Yuan and
Runsheng Wang and
Ru Huang and
Dimin Niu and
Hongzhong Zheng and
Zhichao Lu and
Liang Zhao and
Meng{-}Fan Marvin Chang and
Tianchan Guan and
Xin Si},
title = {Enabling High-Quality Uncertainty Quantification in a {PIM} Designed
for Bayesian Neural Network},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2022, Seoul, South Korea, April 2-6, 2022},
pages = {1043--1055},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/HPCA53966.2022.00080},
doi = {10.1109/HPCA53966.2022.00080},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/LiWSZYWHNZLZCGS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GuoZWXXWSY22,
author = {An Guo and
Yongliang Zhou and
Bo Wang and
Tianzhu Xiong and
Chen Xue and
Yufei Wang and
Xin Si and
Jun Yang},
title = {ShareFloat {CIM:} {A} Compute-In-Memory Architecture with Floating-Point
Multiply-and-Accumulate Operations},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2276--2280},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937242},
doi = {10.1109/ISCAS48785.2022.9937242},
timestamp = {Sun, 30 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GuoZWXXWSY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangXLLYFKXHZGW22,
author = {Bo Wang and
Chen Xue and
Han Liu and
Xiang Li and
Anran Yin and
Zhongyuan Feng and
Yuyao Kong and
Tianzhu Xiong and
Haiming Hsu and
Yongliang Zhou and
An Guo and
Yufei Wang and
Jun Yang and
Xin Si},
title = {{SNNIM:} {A} 10T-SRAM based Spiking-Neural-Network-In-Memory architecture
with capacitance computation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {3383--3387},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937272},
doi = {10.1109/ISCAS48785.2022.9937272},
timestamp = {Sun, 30 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangXLLYFKXHZGW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/ChenXS22,
author = {Jinwu Chen and
Tianzhu Xiong and
Xin Si},
title = {A Charge-Digital Hybrid Compute-In-Memory Macro with full precision
8-bit Multiply-Accumulation for Edge Computing Devices},
booktitle = {15th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2022, Penang, Malaysia, December 19-22, 2022},
pages = {153--158},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MCSoC57363.2022.00033},
doi = {10.1109/MCSOC57363.2022.00033},
timestamp = {Thu, 26 Jan 2023 11:35:12 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/ChenXS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SiTHSLWLWLCCSLL21,
author = {Xin Si and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jian{-}Wei Su and
Pei{-}Jung Lu and
Jing{-}Hong Wang and
Ta{-}Wei Liu and
Ssu{-}Yen Wu and
Ruhui Liu and
Yen{-}Chi Chou and
Yen{-}Lin Chung and
William Shih and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Nan{-}Chun Lien and
Wei{-}Chiang Shih and
Yajuan He and
Qiang Li and
Meng{-}Fan Chang},
title = {A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro
With 8-b {MAC} Operation for Edge {AI} Chips},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {9},
pages = {2817--2831},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2021.3073254},
doi = {10.1109/JSSC.2021.3073254},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SiTHSLWLWLCCSLL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/WangYDSXLSGZLCL21,
author = {Linfang Wang and
Wang Ye and
Chunmeng Dou and
Xin Si and
Xiaoxin Xu and
Jing Liu and
Dashan Shang and
Jianfeng Gao and
Feng Zhang and
Yongpan Liu and
Meng{-}Fan Chang and
Qi Liu},
title = {Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage
Division in 2T2R {RRAM} With Input-Dependent Sensing Control},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {68},
number = {5},
pages = {1640--1644},
year = {2021},
url = {https://doi.org/10.1109/TCSII.2021.3067385},
doi = {10.1109/TCSII.2021.3067385},
timestamp = {Fri, 12 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/WangYDSXLSGZLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/ZengZZQDSL21,
author = {Sitao Zeng and
Yuxin Zhang and
Zhiguo Zhu and
Zhaolong Qin and
Chunmeng Dou and
Xin Si and
Qiang Li},
title = {MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in
Memory Architecture for Edge {AI} Devices},
booktitle = {3rd {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2021, Washington, DC, USA, June 6-9, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/AICAS51828.2021.9458438},
doi = {10.1109/AICAS51828.2021.9458438},
timestamp = {Wed, 01 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aicas/ZengZZQDSL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/SiZYC21,
author = {Xin Si and
Yongliang Zhou and
Jun Yang and
Meng{-}Fan Chang},
editor = {Fan Ye and
Ting{-}Ao Tang},
title = {Challenge and Trend of {SRAM} Based Computation-in-Memory Circuits
for {AI} Edge Devices},
booktitle = {14th {IEEE} International Conference on ASIC, {ASICON} 2021, Kunming,
China, October 26-29, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASICON52560.2021.9620429},
doi = {10.1109/ASICON52560.2021.9620429},
timestamp = {Mon, 06 Dec 2021 11:20:15 +0100},
biburl = {https://dblp.org/rec/conf/asicon/SiZYC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/YuZHHCSYL21,
author = {Qiang Yu and
Xiong Zhou and
Kefeng Hu and
Zijian Huang and
Haiwen Chen and
Xin Si and
Jinda Yang and
Qiang Li},
title = {A 9.08 {ENOB} 10b 400MS/s Subranging {SAR} {ADC} with Subsetted {CDAC}
and {PDAS} in 40nm {CMOS}},
booktitle = {47th {ESSCIRC} 2021 - European Solid State Circuits Conference, {ESSCIR}
2021, Grenoble, France, September 13-22, 2021},
pages = {391--394},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ESSCIRC53450.2021.9567859},
doi = {10.1109/ESSCIRC53450.2021.9567859},
timestamp = {Tue, 15 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/esscirc/YuZHHCSYL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangZZQWLZHDSC21,
author = {Yuxin Zhang and
Sitao Zeng and
Zhiguo Zhu and
Zhaolong Qin and
Chen Wang and
Jingjing Li and
Sanfeng Zhang and
Yajuan He and
Chunmeng Dou and
Xin Si and
Meng{-}Fan Chang and
Qiang Li},
title = {A 40nm 1Mb 35.6 {TOPS/W} {MLC} NOR-Flash Based Computation-in-Memory
Structure for Machine Learning},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401600},
doi = {10.1109/ISCAS51556.2021.9401600},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangZZQWLZHDSC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/XiongZKWGWXHSY21,
author = {Tianzhu Xiong and
Yongliang Zhou and
Yuyao Kong and
Bo Wang and
An Guo and
Yufei Wang and
Chen Xue and
Haiming Hsu and
Xin Si and
Jun Yang},
title = {Design Methodology towards High-Precision {SRAM} based Computation-in-Memory
for {AI} Edge Devices},
booktitle = {18th International SoC Design Conference, {ISOCC} 2021, Jeju Island,
South Korea, Republic of, October 6-9, 2021},
pages = {195--196},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISOCC53507.2021.9613913},
doi = {10.1109/ISOCC53507.2021.9613913},
timestamp = {Sun, 30 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/XiongZKWGWXHSY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GuoYSHLTWLCLWY21,
author = {Ruiqi Guo and
Zhiheng Yue and
Xin Si and
Te Hu and
Hao Li and
Limei Tang and
Yabing Wang and
Leibo Liu and
Meng{-}Fan Chang and
Qiang Li and
Shaojun Wei and
Shouyi Yin},
title = {15.4 {A} 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor
Using Bit-Level-Sparsity-Based Optimization and Variable-Precision
Quantization},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {242--244},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365989},
doi = {10.1109/ISSCC42613.2021.9365989},
timestamp = {Wed, 25 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/GuoYSHLTWLCLWY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SuCLLLWCHRPLCSL21,
author = {Jian{-}Wei Su and
Yen{-}Chi Chou and
Ruhui Liu and
Ta{-}Wei Liu and
Pei{-}Jung Lu and
Ping{-}Chun Wu and
Yen{-}Lin Chung and
Li{-}Yang Hung and
Jin{-}Sheng Ren and
Tianlong Pan and
Sih{-}Han Li and
Shih{-}Chieh Chang and
Shyh{-}Shyuan Sheu and
Wei{-}Chung Lo and
Chih{-}I Wu and
Xin Si and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {16.3 {A} 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision
for {AI} Edge Chips},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2021,
San Francisco, CA, USA, February 13-22, 2021},
pages = {250--252},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISSCC42613.2021.9365984},
doi = {10.1109/ISSCC42613.2021.9365984},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SuCLLLWCHRPLCSL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ucet/WangZWXKS21,
author = {Yufei Wang and
Yongliang Zhou and
Bo Wang and
Tianzhu Xiong and
Yuyao Kong and
Xin Si},
title = {Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory
for {AI} Edge Devices},
booktitle = {International Conference on UK-China Emerging Technologies, {UCET}
2021, Chengdu, China, November 4-6, 2021},
pages = {47--52},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/UCET54125.2021.9674995},
doi = {10.1109/UCET54125.2021.9674995},
timestamp = {Wed, 26 Jan 2022 22:30:07 +0100},
biburl = {https://dblp.org/rec/conf/ucet/WangZWXKS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SiLYLHTLCCTHWCW20,
author = {Xin Si and
Rui Liu and
Shimeng Yu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Qiang Li and
Meng{-}Fan Chang and
Jia{-}Jing Chen and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Yen{-}Cheng Chiu and
Wei{-}Chen Wei and
Ssu{-}Yen Wu and
Xiaoyu Sun},
title = {A Twin-8T {SRAM} Computation-in-Memory Unit-Macro for Multibit CNN-Based
{AI} Edge Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {1},
pages = {189--202},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2019.2952773},
doi = {10.1109/JSSC.2019.2952773},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SiLYLHTLCCTHWCW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChiuZCSLTSHWWHS20,
author = {Yen{-}Cheng Chiu and
Zhixiao Zhang and
Jia{-}Jing Chen and
Xin Si and
Ruhui Liu and
Yung{-}Ning Tu and
Jian{-}Wei Su and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Je{-}Min Hung and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Chih{-}I Wu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory
Unit-Macro for CNN-Based {AI} Edge Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {10},
pages = {2790--2801},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2020.3005754},
doi = {10.1109/JSSC.2020.3005754},
timestamp = {Tue, 06 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/ChiuZCSLTSHWWHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/YueYFHZSLCLYL20,
author = {Jinshan Yue and
Zhe Yuan and
Xiaoyu Feng and
Yifan He and
Zhixiao Zhang and
Xin Si and
Ruhui Liu and
Meng{-}Fan Chang and
Xueqing Li and
Huazhong Yang and
Yongpan Liu},
title = {14.3 {A} 65nm Computing-in-Memory-Based {CNN} Processor with 2.9-to-35.8TOPS/W
System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling
Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {234--236},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062958},
doi = {10.1109/ISSCC19947.2020.9062958},
timestamp = {Sat, 18 Apr 2020 17:41:44 +0200},
biburl = {https://dblp.org/rec/conf/isscc/YueYFHZSLCLYL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SuSCCHTLLLWZJHL20,
author = {Jian{-}Wei Su and
Xin Si and
Yen{-}Chi Chou and
Ting{-}Wei Chang and
Wei{-}Hsing Huang and
Yung{-}Ning Tu and
Ruhui Liu and
Pei{-}Jung Lu and
Ta{-}Wei Liu and
Jing{-}Hong Wang and
Zhixiao Zhang and
Hongwu Jiang and
Shanshi Huang and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Heng{-}Yuan Lee and
Shih{-}Chieh Chang and
Shimeng Yu and
Meng{-}Fan Chang},
title = {15.2 {A} 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T
{SRAM} Compute-in-Memory Macro for {AI} Edge Chips},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {240--242},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062949},
doi = {10.1109/ISSCC19947.2020.9062949},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SuSCCHTLLLWZJHL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SiTHSLWLWLCZSWL20,
author = {Xin Si and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jian{-}Wei Su and
Pei{-}Jung Lu and
Jing{-}Hong Wang and
Ta{-}Wei Liu and
Ssu{-}Yen Wu and
Ruhui Liu and
Yen{-}Chi Chou and
Zhixiao Zhang and
Syuan{-}Hao Sie and
Wei{-}Chen Wei and
Yun{-}Chen Lo and
Tai{-}Hsing Wen and
Tzu{-}Hsiang Hsu and
Yen{-}Kai Chen and
William Shih and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Nan{-}Chun Lien and
Wei{-}Chiang Shih and
Yajuan He and
Qiang Li and
Meng{-}Fan Chang},
title = {15.5 {A} 28nm 64Kb 6T {SRAM} Computing-in-Memory Macro with 8b {MAC}
Operation for {AI} Edge Chips},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {246--248},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9062995},
doi = {10.1109/ISSCC19947.2020.9062995},
timestamp = {Wed, 09 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/SiTHSLWLWLCZSWL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/ZhangSSRC19,
author = {Zhixiao Zhang and
Xin Si and
Srivatsa Srinivasa and
Akshay Krishna Ramanathan and
Meng{-}Fan Chang},
title = {Recent Advances in Compute-in-Memory Support for {SRAM} Using Monolithic
3-D Integration},
journal = {{IEEE} Micro},
volume = {39},
number = {6},
pages = {28--37},
year = {2019},
url = {https://doi.org/10.1109/MM.2019.2946489},
doi = {10.1109/MM.2019.2946489},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/micro/ZhangSSRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SiKCLSLYYLC19,
author = {Xin Si and
Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xiaoyu Sun and
Rui Liu and
Shimeng Yu and
Hiroyuki Yamauchi and
Qiang Li and
Meng{-}Fan Chang},
title = {A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully
Parallel Product-Sum Operation for Binarized {DNN} Edge Processors},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {11},
pages = {4172--4185},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2928043},
doi = {10.1109/TCSI.2019.2928043},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/SiKCLSLYYLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZWSZZ19,
author = {Yajuan He and
Jiubai Zhang and
Xiaoqing Wu and
Xin Si and
Shaowei Zhen and
Bo Zhang},
title = {A Half-Select Disturb-Free 11T {SRAM} Cell With Built-In Write/Read-Assist
Scheme for Ultralow-Voltage Operations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {10},
pages = {2344--2353},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2919104},
doi = {10.1109/TVLSI.2019.2919104},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZWSZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/SiQCXSZLSLCW19,
author = {Xin Si and
He Qian and
Meng{-}Fan Chang and
Cheng{-}Xin Xue and
Jian{-}Wei Su and
Zhixiao Zhang and
Sih{-}Han Li and
Shyh{-}Shyuan Sheu and
Heng{-}Yuan Lee and
Ping{-}Cheng Chen and
Huaqiang Wu},
title = {Circuit Design Challenges in Computing-in-Memory for {AI} Edge Devices},
booktitle = {13th {IEEE} International Conference on ASIC, {ASICON} 2019, Chongqing,
China, October 29 - November 1, 2019},
pages = {1--4},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ASICON47005.2019.8983627},
doi = {10.1109/ASICON47005.2019.8983627},
timestamp = {Wed, 12 Feb 2020 16:13:42 +0100},
biburl = {https://dblp.org/rec/conf/asicon/SiQCXSZLSLCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/ZhangCSTSHWWCHS19,
author = {Zhixiao Zhang and
Jia{-}Jing Chen and
Xin Si and
Yung{-}Ning Tu and
Jian{-}Wei Su and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Wei{-}Chen Wei and
Yen{-}Cheng Chiu and
Je{-}Min Hong and
Shyh{-}Shyuan Sheu and
Sih{-}Han Li and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Meng{-}Fan Chang},
title = {A 55nm 1-to-8 bit Configurable 6T {SRAM} based Computing-in-Memory
Unit-Macro for CNN-based {AI} Edge Processors},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2019, Macau,
SAR, China, November 4-6, 2019},
pages = {217--218},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/A-SSCC47793.2019.9056933},
doi = {10.1109/A-SSCC47793.2019.9056933},
timestamp = {Sun, 19 Apr 2020 17:47:11 +0200},
biburl = {https://dblp.org/rec/conf/asscc/ZhangCSTSHWWCHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SiCTHWCWWSLYLHT19,
author = {Xin Si and
Jia{-}Jing Chen and
Yung{-}Ning Tu and
Wei{-}Hsing Huang and
Jing{-}Hong Wang and
Yen{-}Cheng Chiu and
Wei{-}Chen Wei and
Ssu{-}Yen Wu and
Xiaoyu Sun and
Rui Liu and
Shimeng Yu and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Kea{-}Tiong Tang and
Qiang Li and
Meng{-}Fan Chang},
title = {A Twin-8T {SRAM} Computation-In-Memory Macro for Multiple-Bit CNN-Based
Machine Learning},
booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
San Francisco, CA, USA, February 17-21, 2019},
pages = {396--398},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISSCC.2019.8662392},
doi = {10.1109/ISSCC.2019.8662392},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SiCTHWCWWSLYLHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuPSKSCLCY18,
author = {Rui Liu and
Xiaochen Peng and
Xiaoyu Sun and
Win{-}San Khwa and
Xin Si and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Meng{-}Fan Chang and
Shimeng Yu},
title = {Parallelizing {SRAM} arrays with customized bit-cell for binary neural
networks},
booktitle = {Proceedings of the 55th Annual Design Automation Conference, {DAC}
2018, San Francisco, CA, USA, June 24-29, 2018},
pages = {21:1--21:6},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3195970.3196089},
doi = {10.1145/3195970.3196089},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiuPSKSCLCY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KhwaCLSYSLCLYC18,
author = {Win{-}San Khwa and
Jia{-}Jing Chen and
Jia{-}Fang Li and
Xin Si and
En{-}Yu Yang and
Xiaoyu Sun and
Rui Liu and
Pai{-}Yu Chen and
Qiang Li and
Shimeng Yu and
Meng{-}Fan Chang},
title = {A 65nm 4Kb algorithm-dependent computing-in-memory {SRAM} unit-macro
with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for
binary {DNN} edge processors},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {496--498},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310401},
doi = {10.1109/ISSCC.2018.8310401},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KhwaCLSYSLCLYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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