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ORCIDBibTeX records: Scott C. Smith
@article{DBLP:journals/access/DasHSG23,
author = {Hritom Das and
Ali Ahmad Haidous and
Scott C. Smith and
Na Gong},
title = {Approximate Memory for Low-Power Video Applications},
journal = {{IEEE} Access},
volume = {11},
pages = {57735--57744},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3283409},
doi = {10.1109/ACCESS.2023.3283409},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/DasHSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/KhodosevychBSS23,
author = {Danylo Khodosevych and
Alexander C. Bodoh and
Ashiq A. Sakib and
Scott C. Smith},
title = {Combining Relaxation With NCL{\_}X for Enhanced Optimization of Asynchronous
Null Convention Logic Circuits},
journal = {{IEEE} Access},
volume = {11},
pages = {104688--104699},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3318132},
doi = {10.1109/ACCESS.2023.3318132},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/KhodosevychBSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/SparkmanSD22,
author = {Brett Sparkman and
Scott C. Smith and
Jia Di},
title = {Built-In Self-Test for Multi-Threshold {NULL} Convention Logic Asynchronous
Circuits using Pipeline Stage Parallelism},
journal = {J. Electron. Test.},
volume = {38},
number = {3},
pages = {321--334},
year = {2022},
url = {https://doi.org/10.1007/s10836-022-06007-w},
doi = {10.1007/S10836-022-06007-W},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/SparkmanSD22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/PonugotiSSM22,
author = {Kushal K. Ponugoti and
Sudarshan K. Srinivasan and
Scott C. Smith and
Nimish Mathure},
title = {Illegal Trojan design and detection in asynchronous {NULL} Convention
Logic and Sleep Convention Logic circuits},
journal = {{IET} Comput. Digit. Tech.},
volume = {16},
number = {5-6},
pages = {172--182},
year = {2022},
url = {https://doi.org/10.1049/cdt2.12047},
doi = {10.1049/CDT2.12047},
timestamp = {Mon, 05 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cdt/PonugotiSSM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iotj/FuLLSW21,
author = {Jingyan Fu and
Zhiheng Liao and
Jianqing Liu and
Scott C. Smith and
Jinhui Wang},
title = {Memristor-Based Variation-Enabled Differentially Private Learning
Systems for Edge Computing in IoT},
journal = {{IEEE} Internet Things J.},
volume = {8},
number = {12},
pages = {9672--9682},
year = {2021},
url = {https://doi.org/10.1109/JIOT.2020.3023623},
doi = {10.1109/JIOT.2020.3023623},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iotj/FuLLSW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DasHSG21,
author = {Hritom Das and
Ali Ahmad Haidous and
Scott C. Smith and
Na Gong},
title = {Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {10},
pages = {1693--1706},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2021.3098533},
doi = {10.1109/TVLSI.2021.3098533},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DasHSG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isgt/AhnKSYR21,
author = {BoHyun Ahn and
Taesic Kim and
Scott C. Smith and
Young{-}Woo Youn and
Myung{-}Hyo Ryu},
title = {Security Threat Modeling for Power Transformers in Cyber-Physical
Environments},
booktitle = {{IEEE} Power {\&} Energy Society Innovative Smart Grid Technologies
Conference, {ISGT} 2021, Washington, DC, USA, February 16-18, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISGT49243.2021.9372271},
doi = {10.1109/ISGT49243.2021.9372271},
timestamp = {Thu, 25 Mar 2021 12:12:08 +0100},
biburl = {https://dblp.org/rec/conf/isgt/AhnKSYR21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrtip/JalilSG20,
author = {Nauman Jalil and
Scott C. Smith and
Roger Green},
title = {Performance optimization of rotation-tolerant Viola-Jones-based blackbird
detection},
journal = {J. Real Time Image Process.},
volume = {17},
number = {3},
pages = {471--478},
year = {2020},
url = {https://doi.org/10.1007/s11554-018-0795-7},
doi = {10.1007/S11554-018-0795-7},
timestamp = {Fri, 19 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrtip/JalilSG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcc/AliJKBGSKLZ20,
author = {Sahibzada Muhammad Ali and
Muhammad Jawad and
Muhammad Usman Shahid Khan and
Kashif Bilal and
Jacob Glower and
Scott C. Smith and
Samee U. Khan and
Keqin Li and
Albert Y. Zomaya},
title = {An Ancillary Services Model for Data Centers and Power Systems},
journal = {{IEEE} Trans. Cloud Comput.},
volume = {8},
number = {4},
pages = {1176--1188},
year = {2020},
url = {https://doi.org/10.1109/TCC.2017.2700838},
doi = {10.1109/TCC.2017.2700838},
timestamp = {Tue, 10 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcc/AliJKBGSKLZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PonugotiSS20,
author = {Kushal K. Ponugoti and
Sudarshan K. Srinivasan and
Scott C. Smith},
title = {Hardware Trojan Design and Detection in Asynchronous {NCL} Circuits},
booktitle = {27th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2020, Glasgow, Scotland, UK, November 23-25, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICECS49266.2020.9294946},
doi = {10.1109/ICECS49266.2020.9294946},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icecsys/PonugotiSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SakibS20,
author = {Ashiq A. Sakib and
Scott C. Smith},
title = {Implementation of Static {NCL} Threshold Gates Using Emerging {CNTFET}
Technology},
booktitle = {27th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2020, Glasgow, Scotland, UK, November 23-25, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICECS49266.2020.9294823},
doi = {10.1109/ICECS49266.2020.9294823},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SakibS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/LeSS20,
author = {Son N. Le and
Sudarshan K. Srinivasan and
Scott C. Smith},
title = {Exploiting Dual-Rail Register Invariants for Equivalence Verification
of {NCL} Circuits},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {21--24},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184477},
doi = {10.1109/MWSCAS48704.2020.9184477},
timestamp = {Mon, 21 Sep 2020 12:35:49 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/LeSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/LeSS20a,
author = {Son N. Le and
Sudarshan K. Srinivasan and
Scott C. Smith},
title = {Formal Verification of Completion-Completeness for {NCL} Circuits},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {25--28},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184603},
doi = {10.1109/MWSCAS48704.2020.9184603},
timestamp = {Mon, 21 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/LeSS20a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/JalilS20,
author = {Nauman Jalil and
Scott C. Smith},
title = {Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply
and Accumulate Unit},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {33--36},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184639},
doi = {10.1109/MWSCAS48704.2020.9184639},
timestamp = {Mon, 21 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/JalilS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/SakibAS20,
author = {Ashiq A. Sakib and
Abir A. Akib and
Scott C. Smith},
title = {Implementation of FinFET Based Static {NCL} Threshold Gates: An Analysis
of Design Choice},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {37--40},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184629},
doi = {10.1109/MWSCAS48704.2020.9184629},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/SakibAS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SparkmanSD20,
author = {Brett Sparkman and
Scott C. Smith and
Jia Di},
title = {Built-In Self-Test for Multi-Threshold {NULL} Convention Logic Asynchronous
Circuits},
booktitle = {38th {IEEE} {VLSI} Test Symposium, {VTS} 2020, San Diego, CA, USA,
April 5-8, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VTS48691.2020.9107627},
doi = {10.1109/VTS48691.2020.9107627},
timestamp = {Thu, 25 Jun 2020 15:32:49 +0200},
biburl = {https://dblp.org/rec/conf/vts/SparkmanSD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SakibSS19,
author = {Ashiq A. Sakib and
Scott C. Smith and
Sudarshan K. Srinivasan},
title = {Formal Modeling and Verification of {PCHB} Asynchronous Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {12},
pages = {2911--2924},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2937087},
doi = {10.1109/TVLSI.2019.2937087},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SakibSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HossainSSS19,
author = {Mousam Hossain and
Ashiq A. Sakib and
Sudarshan K. Srinivasan and
Scott C. Smith},
title = {An Equivalence Verification Methodology for Asynchronous Sleep Convention
Logic Circuits},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702098},
doi = {10.1109/ISCAS.2019.8702098},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HossainSSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/SakibSS18,
author = {Ashiq A. Sakib and
Scott C. Smith and
Sudarshan K. Srinivasan},
title = {An Equivalence Verification Methodology for Combinational Asynchronous
{PCHB} Circuits},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {767--770},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8624068},
doi = {10.1109/MWSCAS.2018.8624068},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/SakibSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/Soufizadeh-Balaneji17,
author = {Nasim Soufizadeh{-}Balaneji and
Scott C. Smith},
title = {Analysis and design of {CMOS} resettable C-elements},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {104--107},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8052871},
doi = {10.1109/MWSCAS.2017.8052871},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/Soufizadeh-Balaneji17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/SakibSS17,
author = {Ashiq A. Sakib and
Scott C. Smith and
Sudarshan K. Srinivasan},
title = {Formal modeling and verification for pre-charge half buffer gates
and circuits},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {519--522},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8052974},
doi = {10.1109/MWSCAS.2017.8052974},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/SakibSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/RogersKS17,
author = {Paul Rogers and
Rajesh Kavasseri and
Scott C. Smith},
title = {An FPGA-in-the-loop approach for {HDL} motor controller verification},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2017, Cancun, Mexico, December 4-6, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/RECONFIG.2017.8279774},
doi = {10.1109/RECONFIG.2017.8279774},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/RogersKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParsanSA16,
author = {Farhad Alibeygi Parsan and
Scott C. Smith and
Waleed K. Al{-}Assadi},
title = {Design for Testability of Sleep Convention Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {743--753},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2419816},
doi = {10.1109/TVLSI.2015.2419816},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParsanSA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/RogersKS16,
author = {Paul Rogers and
Rajesh Kavasseri and
Scott C. Smith},
editor = {Peter M. Athanas and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Ron Sass},
title = {An FPGA-based design for joint control and monitoring of permanent
magnet synchronous motors},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ReConFig.2016.7857152},
doi = {10.1109/RECONFIG.2016.7857152},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/RogersKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParsanAS14,
author = {Farhad Alibeygi Parsan and
Waleed K. Al{-}Assadi and
Scott C. Smith},
title = {Gate Mapping Automation for Asynchronous {NULL} Convention Logic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {1},
pages = {99--112},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2012.2231889},
doi = {10.1109/TVLSI.2012.2231889},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParsanAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/WijayasekaraSS14,
author = {Vidura Wijayasekara and
Sudarshan K. Srinivasan and
Scott C. Smith},
title = {Equivalence verification for {NULL} Convention Logic {(NCL)} circuits},
booktitle = {32nd {IEEE} International Conference on Computer Design, {ICCD} 2014,
Seoul, South Korea, October 19-22, 2014},
pages = {195--201},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ICCD.2014.6974681},
doi = {10.1109/ICCD.2014.6974681},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/WijayasekaraSS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ParsanZS14,
author = {Farhad Alibeygi Parsan and
J. Zhao and
Scott C. Smith},
title = {{SCL} design of a pipelined 8051 {ALU}},
booktitle = {{IEEE} 57th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2014, College Station, TX, USA, August 3-6, 2014},
pages = {885--888},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/MWSCAS.2014.6908557},
doi = {10.1109/MWSCAS.2014.6908557},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ParsanZS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/HindsSDS13,
author = {Michael Hinds and
Brett Sparkman and
Jia Di and
Scott C. Smith},
title = {An Asynchronous Advanced Encryption Standard Core Design for Energy
Efficiency},
journal = {J. Low Power Electron.},
volume = {9},
number = {2},
pages = {175--188},
year = {2013},
url = {https://doi.org/10.1166/jolpe.2013.1251},
doi = {10.1166/JOLPE.2013.1251},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/HindsSDS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/CilioLPDTS13,
author = {Washington Cilio and
Michael Linder and
Chris Porter and
Jia Di and
Dale R. Thompson and
Scott C. Smith},
title = {Mitigating power- and timing-based side-channel attacks using dual-spacer
dual-rail delay-insensitive asynchronous logic},
journal = {Microelectron. J.},
volume = {44},
number = {3},
pages = {258--269},
year = {2013},
url = {https://doi.org/10.1016/j.mejo.2012.12.001},
doi = {10.1016/J.MEJO.2012.12.001},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/CilioLPDTS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/PalangpourS13,
author = {Parviz Palangpour and
Scott C. Smith},
title = {Sleep Convention Logic using partially slept function blocks},
booktitle = {{IEEE} 56th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2013, Columbus, OH, USA, August 4-7, 2013},
pages = {17--20},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/MWSCAS.2013.6674574},
doi = {10.1109/MWSCAS.2013.6674574},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/PalangpourS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/VaradharajanAAS13,
author = {Pragadesh Varadharajan and
Waleed K. Al{-}Assadi and
Shabab F. Alam and
Scott C. Smith},
title = {Quantum-dot cellular automaton of asynchronous Null Convention Logic
multiplier design},
booktitle = {{IEEE} 56th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2013, Columbus, OH, USA, August 4-7, 2013},
pages = {813--816},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/MWSCAS.2013.6674773},
doi = {10.1109/MWSCAS.2013.6674773},
timestamp = {Sun, 29 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/VaradharajanAAS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/async/ReeseST12,
author = {Robert B. Reese and
Scott C. Smith and
Mitchell A. Thornton},
editor = {Jens Spars{\o} and
Montek Singh and
Pascal Vivet},
title = {Uncle - An {RTL} Approach to Asynchronous Design},
booktitle = {18th {IEEE} International Symposium on Asynchronous Circuits and Systems,
{ASYNC} 2012, Kgs. Lyngby, Denmark, May 7-9, 2012},
pages = {65--72},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ASYNC.2012.14},
doi = {10.1109/ASYNC.2012.14},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/async/ReeseST12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ParsanS12,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
title = {{CMOS} implementation comparison of {NCL} gates},
booktitle = {55th {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2012, Boise, ID, USA, August 5-8, 2012},
pages = {394--397},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/MWSCAS.2012.6292040},
doi = {10.1109/MWSCAS.2012.6292040},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/ParsanS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParsanS12,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {{CMOS} implementation of static threshold gates with hysteresis: {A}
new approach},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {41--45},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379003},
doi = {10.1109/VLSI-SOC.2012.6379003},
timestamp = {Tue, 06 Sep 2022 16:02:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParsanS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ParsanS12a,
author = {Farhad Alibeygi Parsan and
Scott C. Smith},
editor = {Andreas Burg and
Ayse K. Coskun and
Matthew R. Guthaus and
Srinivas Katkoori and
Ricardo Reis},
title = {{CMOS} Implementation of Threshold Gates with Hysteresis},
booktitle = {VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design -
20th {IFIP} {WG} 10.5/IEEE International Conference on Very Large
Scale Integration, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10,
2012, Revised Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {418},
pages = {196--216},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-45073-0\_11},
doi = {10.1007/978-3-642-45073-0\_11},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ParsanS12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/te/SmithAD10,
author = {Scott C. Smith and
Waleed K. Al{-}Assadi and
Jia Di},
title = {Integrating Asynchronous Digital Design Into the Computer Engineering
Curriculum},
journal = {{IEEE} Trans. Educ.},
volume = {53},
number = {3},
pages = {349--357},
year = {2010},
url = {https://doi.org/10.1109/TE.2009.2021391},
doi = {10.1109/TE.2009.2021391},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/te/SmithAD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/SmithRD10,
author = {Scott C. Smith and
David Roclin and
Jia Di},
editor = {Hamid R. Arabnia and
Ashu M. G. Solo},
title = {Delay-Insensitive Cell Matrix},
booktitle = {Proceedings of the 2010 International Conference on Computer Design,
{CDES} 2010, July 12-15, 2010, Las Vegas Nevada, {USA}},
pages = {67--73},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Thu, 08 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cdes/SmithRD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:series/synthesis/2009Smith,
author = {Scott C. Smith and
Jia Di},
title = {Designing Asynchronous Circuits using {NULL} Convention Logic {(NCL)}},
series = {Synthesis Lectures on Digital Circuits and Systems},
publisher = {Morgan {\&} Claypool Publishers},
year = {2009},
url = {https://doi.org/10.2200/S00202ED1V01Y200907DCS023},
doi = {10.2200/S00202ED1V01Y200907DCS023},
isbn = {978-3-031-79799-6},
timestamp = {Fri, 20 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/series/synthesis/2009Smith.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3dic/HollosiZNXDS09,
author = {Brent Hollosi and
Tao Zhang and
Ravi Sankar Parameswaran Nair and
Yuan Xie and
Jia Di and
Scott C. Smith},
title = {Investigation and comparison of thermal distribution in synchronous
and asynchronous 3D ICs},
booktitle = {{IEEE} International Conference on 3D System Integration, 3DIC 2009,
San Francisco, California, USA, 28-30 September 2009},
pages = {1--5},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/3DIC.2009.5306544},
doi = {10.1109/3DIC.2009.5306544},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/3dic/HollosiZNXDS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/NairSD09,
author = {Ravi Sankar Parameswaran Nair and
Scott C. Smith and
Jia Di},
editor = {Hamid R. Arabnia and
Ashu M. G. Solo},
title = {Delay-Insensitive Ternary Logic},
booktitle = {Proceedings of the 2009 International Conference on Computer Design,
{CDES} 2009, July 13-16, 2009, Las Vegas Nevada, {USA}},
pages = {3--0},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Fri, 30 Oct 2009 13:41:31 +0100},
biburl = {https://dblp.org/rec/conf/cdes/NairSD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/PalangpourVS09,
author = {Parviz Palangpour and
Ganesh K. Venayagamoorthy and
Scott C. Smith},
editor = {Hamid R. Arabnia and
Ashu M. G. Solo},
title = {Particle Swarm Optimization: {A} Hardware Implementation},
booktitle = {Proceedings of the 2009 International Conference on Computer Design,
{CDES} 2009, July 13-16, 2009, Las Vegas Nevada, {USA}},
pages = {134--139},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Wed, 19 May 2010 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cdes/PalangpourVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itsc/WuS09,
author = {Jingxian Wu and
Scott C. Smith},
title = {Integrated software-hardware design for ultra-low power infrastructure
monitoring},
booktitle = {12th International {IEEE} Conference on Intelligent Transportation
Systems, {ITSC} 2009, St. Louis, MO, USA, October 5-7, 2009},
pages = {1--8},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ITSC.2009.5309696},
doi = {10.1109/ITSC.2009.5309696},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itsc/WuS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/BaileyZFDS08,
author = {Andrew Bailey and
Ahmad Al Zahrani and
Guoyuan Fu and
Jia Di and
Scott C. Smith},
title = {Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power},
journal = {J. Low Power Electron.},
volume = {4},
number = {3},
pages = {337--348},
year = {2008},
url = {https://doi.org/10.1166/jolpe.2008.181},
doi = {10.1166/JOLPE.2008.181},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/BaileyZFDS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/eaai/VenayagamoorthySS07,
author = {Ganesh K. Venayagamoorthy and
Scott C. Smith and
Gaurav Singhal},
title = {Particle swarm-based optimal partitioning algorithm for combinational
{CMOS} circuits},
journal = {Eng. Appl. Artif. Intell.},
volume = {20},
number = {2},
pages = {177--184},
year = {2007},
url = {https://doi.org/10.1016/j.engappai.2006.06.011},
doi = {10.1016/J.ENGAPPAI.2006.06.011},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/eaai/VenayagamoorthySS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/SatagopanBSS07,
author = {Venkat Satagopan and
Bonita Bhaskaran and
Anshul Singh and
Scott C. Smith},
title = {Automated energy calculation and estimation for delay-insensitive
digital circuits},
journal = {Microelectron. J.},
volume = {38},
number = {10-11},
pages = {1095--1107},
year = {2007},
url = {https://doi.org/10.1016/j.mejo.2007.08.004},
doi = {10.1016/J.MEJO.2007.08.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/SatagopanBSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Smith07,
author = {Scott C. Smith},
title = {Design of an {FPGA} Logic Element for Implementing Asynchronous {NULL}
Convention Logic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {6},
pages = {672--683},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.898726},
doi = {10.1109/TVLSI.2007.898726},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Smith07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SatagopanBASK07,
author = {Venkat Satagopan and
Bonita Bhaskaran and
Waleed K. Al{-}Assadi and
Scott C. Smith and
Sindhu Kakarla},
title = {{DFT} Techniques and Automation for Asynchronous {NULL} Conventional
Logic Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {15},
number = {10},
pages = {1155--1159},
year = {2007},
url = {https://doi.org/10.1109/TVLSI.2007.903945},
doi = {10.1109/TVLSI.2007.903945},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SatagopanBASK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Smith07,
author = {Scott C. Smith},
editor = {Andr{\'{e}} DeHon and
Mike Hutton},
title = {Design of a logic element for implementing an asynchronous {FPGA}},
booktitle = {Proceedings of the {ACM/SIGDA} 15th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2007, Monterey, California, USA,
February 18-20, 2007},
pages = {13--22},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1216919.1216922},
doi = {10.1145/1216919.1216922},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Smith07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Smith06,
author = {Scott C. Smith},
title = {Speedup of {NULL} convention digital circuits using {NULL} cycle reduction},
journal = {J. Syst. Archit.},
volume = {52},
number = {7},
pages = {411--422},
year = {2006},
url = {https://doi.org/10.1016/j.sysarc.2005.12.002},
doi = {10.1016/J.SYSARC.2005.12.002},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/Smith06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Smith05,
author = {Scott C. Smith},
title = {Development of a large word-width high-speed asynchronous multiply
and accumulate unit},
journal = {Integr.},
volume = {39},
number = {1},
pages = {12--28},
year = {2005},
url = {https://doi.org/10.1016/j.vlsi.2004.11.001},
doi = {10.1016/J.VLSI.2004.11.001},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Smith05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/BhaskaranSS05,
author = {Bonita Bhaskaran and
Venkat Satagopan and
Scott C. Smith},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
Yiming Li and
Salam N. Salloum and
Jos{\'{e}} G. Delgado{-}Frias},
title = {High-Speed Energy Estimation for Delay-Insensitive Circuits},
booktitle = {Proceedings of the 2005 International Conference on Computer Design,
{CDES} 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
pages = {35--41},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Sat, 26 Jan 2008 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cdes/BhaskaranSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/BhaskaranSAS05,
author = {Bonita Bhaskaran and
Venkat Satagopan and
Waleed K. Al{-}Assadi and
Scott C. Smith},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
Yiming Li and
Salam N. Salloum and
Jos{\'{e}} G. Delgado{-}Frias},
title = {Implementation of Design For Test for Asynchronous {NCL} Designs},
booktitle = {Proceedings of the 2005 International Conference on Computer Design,
{CDES} 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
pages = {78--84},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Thu, 30 Jan 2014 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cdes/BhaskaranSAS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/SinghS05,
author = {Anshul Singh and
Scott C. Smith},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
Yiming Li and
Salam N. Salloum and
Jos{\'{e}} G. Delgado{-}Frias},
title = {Using a {VHDL} Testbench for Transistor-Level Simulation and Energy
Calculation},
booktitle = {Proceedings of the 2005 International Conference on Computer Design,
{CDES} 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
pages = {115--121},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Sat, 26 Jan 2008 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cdes/SinghS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SmithDYFL04,
author = {Scott C. Smith and
Ronald F. DeMara and
Jiann{-}Shiun Yuan and
Dennis Ferguson and
D. Lamb},
title = {Optimization of {NULL} convention self-timed circuits},
journal = {Integr.},
volume = {37},
number = {3},
pages = {135--165},
year = {2004},
url = {https://doi.org/10.1016/j.vlsi.2003.12.004},
doi = {10.1016/J.VLSI.2003.12.004},
timestamp = {Thu, 08 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SmithDYFL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/Smith04a,
author = {Scott C. Smith},
editor = {Hamid R. Arabnia and
Minyi Guo and
Laurence Tianruo Yang},
title = {Designing {NULL} Convention Combinational Circuits to Fully Utilize
Gate-Level Pipelining for Maximum Throughput},
booktitle = {Proceedings of the International Conference on Embedded Systems and
Applications, {ESA} '04 {\&} Proceedings of the International
Conference on VLSI, {VLSI} '04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {407--412},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Fri, 04 Mar 2005 11:26:21 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/Smith04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/Smith04b,
author = {Scott C. Smith},
editor = {Hamid R. Arabnia and
Minyi Guo and
Laurence Tianruo Yang},
title = {Design of a {NULL} Convention Self-Timed Divider},
booktitle = {Proceedings of the International Conference on Embedded Systems and
Applications, {ESA} '04 {\&} Proceedings of the International
Conference on VLSI, {VLSI} '04, June 21-24, 2004, Las Vegas, Nevada,
{USA}},
pages = {447--453},
publisher = {{CSREA} Press},
year = {2004},
timestamp = {Tue, 23 Nov 2004 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/Smith04b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BandapatiSC03,
author = {Satish K. Bandapati and
Scott C. Smith and
Minsu Choi},
title = {Design and Characterization of Null Convention Self-Timed Multipliers},
journal = {{IEEE} Des. Test Comput.},
volume = {20},
number = {6},
pages = {26--36},
year = {2003},
url = {https://doi.org/10.1109/MDT.2003.1246161},
doi = {10.1109/MDT.2003.1246161},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BandapatiSC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/amcc/SmithF03,
author = {Scott C. Smith and
James Fisher},
title = {On generating random systems: a gramian approach},
booktitle = {American Control Conference, {ACC} 2003, Denver, CO, USA, June 4-6
2003},
pages = {2743--2748},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ACC.2003.1243494},
doi = {10.1109/ACC.2003.1243494},
timestamp = {Mon, 06 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/amcc/SmithF03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Smith03,
author = {Scott C. Smith},
editor = {Hamid R. Arabnia and
Laurence Tianruo Yang},
title = {Completion-Completeness for {NULL} Convention Digital Circuits Utilizing
the Bit-Wise Completion Strategy},
booktitle = {Proceedings of the International Conference on VLSI, {VLSI} '03, June
23 - 26, 2003, Las Vegas, Nevada, {USA}},
pages = {143--149},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Fri, 17 Oct 2003 11:18:22 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Smith03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BandapatiS03,
author = {Satish K. Bandapati and
Scott C. Smith},
editor = {Hamid R. Arabnia and
Laurence Tianruo Yang},
title = {Design and Characterization of {NULL} Convention Arithmetic Logic
Units},
booktitle = {Proceedings of the International Conference on VLSI, {VLSI} '03, June
23 - 26, 2003, Las Vegas, Nevada, {USA}},
pages = {178--184},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Fri, 17 Oct 2003 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BandapatiS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/SmithDYHF02,
author = {Scott C. Smith and
Ronald F. DeMara and
Jiann{-}Shiun Yuan and
M. Hagedorn and
Dennis Ferguson},
title = {{NULL} convention multiply and accumulate unit with conditional rounding,
scaling, and saturation},
journal = {J. Syst. Archit.},
volume = {47},
number = {12},
pages = {977--998},
year = {2002},
url = {https://doi.org/10.1016/S1383-7621(02)00060-7},
doi = {10.1016/S1383-7621(02)00060-7},
timestamp = {Thu, 08 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jsa/SmithDYHF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Smith02,
author = {Scott C. Smith},
title = {Speedup of Self-Timed Digital Systems Using Early Completion},
booktitle = {2002 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2002), 25-26 April 2002, Pittsburgh, PA, {USA}},
pages = {107--116},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISVLSI.2002.1016884},
doi = {10.1109/ISVLSI.2002.1016884},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Smith02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SmithDYHF01,
author = {Scott C. Smith and
Ronald F. DeMara and
Jiann{-}Shiun Yuan and
M. Hagedorn and
Dennis Ferguson},
title = {Delay-insensitive gate-level pipelining},
journal = {Integr.},
volume = {30},
number = {2},
pages = {103--131},
year = {2001},
url = {https://doi.org/10.1016/S0167-9260(01)00013-X},
doi = {10.1016/S0167-9260(01)00013-X},
timestamp = {Thu, 08 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SmithDYHF01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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