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ORCIDBibTeX records: Cliff C. N. Sze
@article{DBLP:journals/ipsj/KnechtelSELS17,
author = {Johann Knechtel and
Ozgur Sinanoglu and
Ibrahim Abe M. Elfadel and
Jens Lienig and
Cliff C. N. Sze},
title = {Large-Scale 3D Chips: Challenges and Solutions for Design Automation,
Testing, and Trustworthy Integration},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {45--62},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.45},
doi = {10.2197/IPSJTSLDM.10.45},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KnechtelSELS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bcb/ZhouKHLS17,
author = {He Zhou and
Sunil P. Khatri and
Jiang Hu and
Frank Liu and
Cliff C. N. Sze},
editor = {Nurit Haspel and
Lenore J. Cowen and
Amarda Shehu and
Tamer Kahveci and
Giuseppe Pozzi},
title = {Fast and Highly Scalable Bayesian {MDP} on a {GPU} Platform},
booktitle = {Proceedings of the 8th {ACM} International Conference on Bioinformatics,
Computational Biology, and Health Informatics, {BCB} 2017, Boston,
MA, USA, August 20-23, 2017},
pages = {158--167},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3107411.3107440},
doi = {10.1145/3107411.3107440},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/bcb/ZhouKHLS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ReimannSR16,
author = {Tiago Reimann and
Cliff C. N. Sze and
Ricardo Reis},
title = {Challenges of cell selection algorithms in industrial high performance
microprocessor designs},
journal = {Integr.},
volume = {52},
pages = {347--354},
year = {2016},
url = {https://doi.org/10.1016/j.vlsi.2015.09.001},
doi = {10.1016/J.VLSI.2015.09.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ReimannSR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bhi/ZhouHKLSY16,
author = {He Zhou and
Jiang Hu and
Sunil P. Khatri and
Frank Liu and
Cliff C. N. Sze and
Mohammadmahdi R. Yousefi},
title = {{GPU} acceleration for Bayesian control of Markovian genetic regulatory
networks},
booktitle = {2016 {IEEE-EMBS} International Conference on Biomedical and Health
Informatics, {BHI} 2016, Las Vegas, NV, USA, February 24-27, 2016},
pages = {304--307},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/BHI.2016.7455895},
doi = {10.1109/BHI.2016.7455895},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/bhi/ZhouHKLSY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ReimannSR16,
author = {Tiago J. Reimann and
Cliff C. N. Sze and
Ricardo Reis},
editor = {Evangeline F. Y. Young and
Mustafa Ozdal},
title = {Cell Selection for High-Performance Designs in an Industrial Design
Flow},
booktitle = {Proceedings of the 2016 on International Symposium on Physical Design,
{ISPD} 2016, Santa Rosa, CA, USA, April 3-6, 2016},
pages = {65--72},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2872334.2872358},
doi = {10.1145/2872334.2872358},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/ReimannSR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DavoodiHOS15,
author = {Azadeh Davoodi and
Jiang Hu and
Muhammet Mustafa Ozdal and
Cliff C. N. Sze},
title = {Guest Editorial: Special Section on Physical Design Techniques for
Advanced Technology Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {4},
pages = {501},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2410671},
doi = {10.1109/TCAD.2015.2410671},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DavoodiHOS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaiDZYNS15,
author = {Yici Cai and
Chao Deng and
Qiang Zhou and
Hailong Yao and
Feifei Niu and
Cliff N. Sze},
title = {Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient
Buffer Insertion},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {1},
pages = {142--155},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2300174},
doi = {10.1109/TVLSI.2014.2300174},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CaiDZYNS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ReimannSR15,
author = {Tiago Reimann and
Cliff C. N. Sze and
Ricardo Reis},
title = {Gate sizing and threshold voltage assignment for high performance
microprocessor designs},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {214--219},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059007},
doi = {10.1109/ASPDAC.2015.7059007},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ReimannSR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KohS14,
author = {Cheng{-}Kok Koh and
Chin Ngai Sze},
title = {Guest Editorial Special Section on Contemporary and Emerging Issues
in Physical Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {4},
pages = {493--494},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2304991},
doi = {10.1109/TCAD.2014.2304991},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KohS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WeiSVLARHTKS14,
author = {Yaoguang Wei and
Cliff C. N. Sze and
Natarajan Viswanathan and
Zhuo Li and
Charles J. Alpert and
Lakshmi N. Reddy and
Andrew D. Huber and
Gustavo E. T{\'{e}}llez and
Douglas Keller and
Sachin S. Sapatnekar},
title = {Techniques for scalable and effective routability evaluation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {17:1--17:37},
year = {2014},
url = {https://doi.org/10.1145/2566663},
doi = {10.1145/2566663},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WeiSVLARHTKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/ZhouRPKQLAS14,
author = {Nancy Y. Zhou and
Phillip J. Restle and
Joseph N. Palumbo and
Joseph N. Kozhaya and
Haifeng Qian and
Zhuo Li and
Charles J. Alpert and
Cliff C. N. Sze},
title = {Pacman: driving nonuniform clock grid loads for low-skew robust clock
network},
booktitle = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
{SLIP} 2014, San Francisco, CA, USA, June 1, 2014},
pages = {3:1--3:5},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1145/2633948.2633953},
doi = {10.1145/2633948.2633953},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/ZhouRPKQLAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2014,
editor = {Cliff C. N. Sze and
Azadeh Davoodi},
title = {International Symposium on Physical Design, ISPD'14, Petaluma, CA,
USA, March 30 - April 02, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2560519},
doi = {10.1145/2560519},
isbn = {978-1-4503-2592-9},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/2014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WeiTWSA13,
author = {Xing Wei and
Wai{-}Chung Tang and
Yu{-}Liang Wu and
Cliff C. N. Sze and
Charles J. Alpert},
title = {Mountain-mover: An intuitive logic shifting heuristic for improving
timing slack violating paths},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {350--355},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509620},
doi = {10.1109/ASPDAC.2013.6509620},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/WeiTWSA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuWSALLV13,
author = {Wen{-}Hao Liu and
Yaoguang Wei and
Cliff C. N. Sze and
Charles J. Alpert and
Zhuo Li and
Yih{-}Lang Li and
Natarajan Viswanathan},
title = {Routing congestion estimation with real design constraints},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {92:1--92:8},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488847},
doi = {10.1145/2463209.2488847},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuWSALLV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WeiLSHAS13,
author = {Yaoguang Wei and
Zhuo Li and
Cliff C. N. Sze and
Shiyan Hu and
Charles J. Alpert and
Sachin S. Sapatnekar},
editor = {Enrico Macii},
title = {{CATALYST:} planning layer directives for effective design closure},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1873--1878},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.373},
doi = {10.7873/DATE.2013.373},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/WeiLSHAS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccS/OsieckiTGJNSS13,
author = {Thomas H. Osiecki and
Min{-}Yu Tsai and
Anne E. Gattiker and
Damir A. Jamsek and
Sani R. Nassif and
William Evan Speight and
Cliff C. N. Sze},
editor = {Vassil Alexandrov and
Michael Lees and
Valeria V. Krzhizhanovskaya and
Jack J. Dongarra and
Peter M. A. Sloot},
title = {Hardware Acceleration of an Efficient and Accurate Proton Therapy
Monte Carlo},
booktitle = {Proceedings of the International Conference on Computational Science,
{ICCS} 2013, Barcelona, Spain, 5-7 June, 2013},
series = {Procedia Computer Science},
volume = {18},
pages = {2241--2250},
publisher = {Elsevier},
year = {2013},
url = {https://doi.org/10.1016/j.procs.2013.05.395},
doi = {10.1016/J.PROCS.2013.05.395},
timestamp = {Wed, 12 Jul 2023 15:16:18 +0200},
biburl = {https://dblp.org/rec/conf/iccS/OsieckiTGJNSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/WardVZSLAP13,
author = {Samuel I. Ward and
Natarajan Viswanathan and
Nancy Y. Zhou and
Cliff C. N. Sze and
Zhuo Li and
Charles J. Alpert and
David Z. Pan},
editor = {J{\"{o}}rg Henkel},
title = {Clock power minimization using structured latch templates and decision
tree induction},
booktitle = {The {IEEE/ACM} International Conference on Computer-Aided Design,
ICCAD'13, San Jose, CA, USA, November 18-21, 2013},
pages = {599--606},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICCAD.2013.6691178},
doi = {10.1109/ICCAD.2013.6691178},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/WardVZSLAP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SzeBJWFZDK13,
author = {Cliff C. N. Sze and
Laleh Behjat and
Nikhil Jayakumar and
Atul Walimbe and
Gregory Ford and
Mark Zwolinski and
Harish Dangat and
Giriraj Kakol},
editor = {Cheng{-}Kok Koh and
Cliff C. N. Sze},
title = {{ISPD} 2013 expert designer/user session (eds)},
booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV,
USA, March 24-27, 2013},
pages = {137},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2451916.2451951},
doi = {10.1145/2451916.2451951},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SzeBJWFZDK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2013,
editor = {Cheng{-}Kok Koh and
Cliff C. N. Sze},
title = {International Symposium on Physical Design, ISPD'13, Stateline, NV,
USA, March 24-27, 2013},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2451916},
doi = {10.1145/2451916},
isbn = {978-1-4503-1954-6},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/2013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TianTYS12,
author = {Haitong Tian and
Wai{-}Chung Tang and
Evangeline F. Y. Young and
Cliff C. N. Sze},
title = {Postgrid Clock Routing for High Performance Microprocessor Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {255--259},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170688},
doi = {10.1109/TCAD.2011.2170688},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TianTYS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiANSVZ12,
author = {Zhuo Li and
Charles J. Alpert and
Gi{-}Joon Nam and
Cliff C. N. Sze and
Natarajan Viswanathan and
Nancy Y. Zhou},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {Guiding a physical design closure system to produce easier-to-route
designs with more predictable timing},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {465--470},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228442},
doi = {10.1145/2228360.2228442},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiANSVZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WeiSVLARHTKS12,
author = {Yaoguang Wei and
Cliff C. N. Sze and
Natarajan Viswanathan and
Zhuo Li and
Charles J. Alpert and
Lakshmi N. Reddy and
Andrew D. Huber and
Gustavo E. T{\'{e}}llez and
Douglas Keller and
Sachin S. Sapatnekar},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {{GLARE:} global and local wiring aware routability evaluation},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {768--773},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228499},
doi = {10.1145/2228360.2228499},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WeiSVLARHTKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ViswanathanASLW12,
author = {Natarajan Viswanathan and
Charles J. Alpert and
Cliff C. N. Sze and
Zhuo Li and
Yaoguang Wei},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {The {DAC} 2012 routability-driven placement contest and benchmark
suite},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {774--782},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228500},
doi = {10.1145/2228360.2228500},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ViswanathanASLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/WeiTWSA12,
author = {Xing Wei and
Wai{-}Chung Tang and
Yu{-}Liang Wu and
Cliff C. N. Sze and
Charles J. Alpert},
editor = {Erik Brunvard and
Ken Stevens and
Joseph R. Cavallaro and
Tong Zhang},
title = {{WRIP:} logic restructuring techniques for wirelength-driven incremental
placement},
booktitle = {Great Lakes Symposium on {VLSI} 2012, GLSVLSI'12, Salt Lake City,
UT, USA, May 3-4, 2012},
pages = {327--332},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2206781.2206861},
doi = {10.1145/2206781.2206861},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/WeiTWSA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AlpertLNSVW12,
author = {Charles J. Alpert and
Zhuo Li and
Gi{-}Joon Nam and
Chin Ngai Sze and
Natarajan Viswanathan and
Samuel I. Ward},
editor = {Alan J. Hu},
title = {Placement: Hot or Not?},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {283--290},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429442},
doi = {10.1145/2429384.2429442},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/AlpertLNSVW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ViswanathanASLW12,
author = {Natarajan Viswanathan and
Charles J. Alpert and
Cliff C. N. Sze and
Zhuo Li and
Yaoguang Wei},
editor = {Alan J. Hu},
title = {{ICCAD-2012} {CAD} contest in design hierarchy aware routability-driven
placement and benchmark suite},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {345--348},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429456},
doi = {10.1145/2429384.2429456},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ViswanathanASLW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/FriedrichPBBDHHKKKLLMNOPQRRRRRRST11,
author = {Joshua Friedrich and
Ruchir Puri and
Uwe Brandt and
Markus B{\"{u}}hler and
Jack DiLullo and
Jeremy Hopkins and
Mozammel Hossain and
Michael A. Kazda and
Joachim Keinert and
Zahi M. Kurzum and
Douglass Lamb and
Alice Lee and
Frank Musante and
Jens Noack and
Peter J. Osler and
Stephen D. Posluszny and
Haifeng Qian and
Shyam Ramji and
Vasant B. Rao and
Lakshmi N. Reddy and
Haoxing Ren and
Thomas E. Rosser and
Benjamin R. Russell and
Cliff C. N. Sze and
Gustavo E. T{\'{e}}llez},
title = {Design methodology for the {IBM} {POWER7} microprocessor},
journal = {{IBM} J. Res. Dev.},
volume = {55},
number = {3},
pages = {9},
year = {2011},
url = {https://doi.org/10.1147/JRD.2011.2105692},
doi = {10.1147/JRD.2011.2105692},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/FriedrichPBBDHHKKKLLMNOPQRRRRRRST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/PapaASLVNM11,
author = {David A. Papa and
Charles J. Alpert and
Cliff C. N. Sze and
Zhuo Li and
Natarajan Viswanathan and
Gi{-}Joon Nam and
Igor L. Markov},
title = {Physical Synthesis with Clock-Network Optimization for Large Systems
on Chips},
journal = {{IEEE} Micro},
volume = {31},
number = {4},
pages = {51--62},
year = {2011},
url = {https://doi.org/10.1109/MM.2011.41},
doi = {10.1109/MM.2011.41},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/PapaASLVNM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ZhouALST11,
author = {Nancy Ying Zhou and
Charles J. Alpert and
Zhuo Li and
Cliff N. Sze and
Louise Trevillyan},
title = {Shedding Physical Synthesis Area Bloat},
journal = {{VLSI} Design},
volume = {2011},
pages = {503025:1--503025:10},
year = {2011},
url = {https://doi.org/10.1155/2011/503025},
doi = {10.1155/2011/503025},
timestamp = {Sat, 24 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsi/ZhouALST11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/MoffittS11,
author = {Michael D. Moffitt and
Chin Ngai Sze},
title = {Wire synthesizable global routing for timing closure},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {545--550},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722249},
doi = {10.1109/ASPDAC.2011.5722249},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/MoffittS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NiuZYCYS11,
author = {Feifei Niu and
Qiang Zhou and
Hailong Yao and
Yici Cai and
Jianlei Yang and
Chin Ngai Sze},
editor = {David Atienza and
Yuan Xie and
Jos{\'{e}} L. Ayala and
Ken S. Stevens},
title = {Obstacle-avoiding and slew-constrained buffered clock tree synthesis
for skew optimization},
booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
Lausanne, Switzerland, May 2-6, 2011},
pages = {199--204},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1973009.1973049},
doi = {10.1145/1973009.1973049},
timestamp = {Sun, 05 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/NiuZYCYS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/Sze11,
author = {Cliff C. N. Sze},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {The future of clock network synthesis},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {270},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105339},
doi = {10.1109/ICCAD.2011.6105339},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/Sze11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/TianTYS11,
author = {Haitong Tian and
Wai{-}Chung Tang and
Evangeline F. Y. Young and
Cliff C. N. Sze},
editor = {Yao{-}Wen Chang and
Jiang Hu},
title = {Grid-to-ports clock routing for high performance microprocessor designs},
booktitle = {Proceedings of the 2011 International Symposium on Physical Design,
{ISPD} 2011, Santa Barbara, California, USA, March 27-30, 2011},
pages = {21--28},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1960397.1960406},
doi = {10.1145/1960397.1960406},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/TianTYS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/WardPLSAS11,
author = {Samuel I. Ward and
David A. Papa and
Zhuo Li and
Cliff N. Sze and
Charles J. Alpert and
Earl E. Swartzlander Jr.},
editor = {Yao{-}Wen Chang and
Jiang Hu},
title = {Quantifying academic placer performance on custom designs},
booktitle = {Proceedings of the 2011 International Symposium on Physical Design,
{ISPD} 2011, Santa Barbara, California, USA, March 27-30, 2011},
pages = {91--98},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1960397.1960420},
doi = {10.1145/1960397.1960420},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/WardPLSAS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/ViswanathanASLNR11,
author = {Natarajan Viswanathan and
Charles J. Alpert and
Cliff C. N. Sze and
Zhuo Li and
Gi{-}Joon Nam and
Jarrod A. Roy},
editor = {Yao{-}Wen Chang and
Jiang Hu},
title = {The {ISPD-2011} routability-driven placement contest and benchmark
suite},
booktitle = {Proceedings of the 2011 International Symposium on Physical Design,
{ISPD} 2011, Santa Barbara, California, USA, March 27-30, 2011},
pages = {141--146},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1960397.1960429},
doi = {10.1145/1960397.1960429},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/ViswanathanASLNR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BanerjeeASNO10,
author = {Shayak Banerjee and
Kanak B. Agarwal and
Chin Ngai Sze and
Sani R. Nassif and
Michael Orshansky},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {A methodology for propagating design tolerances to shape tolerances
for use in manufacturing},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1273--1278},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457002},
doi = {10.1109/DATE.2010.5457002},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/BanerjeeASNO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/LiPAHSSZ10,
author = {Zhuo Li and
David A. Papa and
Charles J. Alpert and
Shiyan Hu and
Weiping Shi and
Cliff C. N. Sze and
Nancy Ying Zhou},
editor = {Prashant Saxena and
Yao{-}Wen Chang},
title = {Ultra-fast interconnect driven cell cloning for minimizing critical
path delay},
booktitle = {Proceedings of the 2010 International Symposium on Physical Design,
{ISPD} 2010, San Francisco, California, USA, March 14-17, 2010},
pages = {75--82},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1735023.1735047},
doi = {10.1145/1735023.1735047},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/LiPAHSSZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Sze10,
author = {Cliff C. N. Sze},
editor = {Prashant Saxena and
Yao{-}Wen Chang},
title = {{ISPD} 2010 high performance clock network synthesis contest: benchmark
suite and results},
booktitle = {Proceedings of the 2010 International Symposium on Physical Design,
{ISPD} 2010, San Francisco, California, USA, March 14-17, 2010},
pages = {143},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1735023.1735058},
doi = {10.1145/1735023.1735058},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/Sze10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SzeRNA09,
author = {Cliff N. Sze and
Phillip J. Restle and
Gi{-}Joon Nam and
Charles J. Alpert},
editor = {Gi{-}Joon Nam and
Prashant Saxena},
title = {Ispd2009 clock network synthesis contest},
booktitle = {Proceedings of the 2009 International Symposium on Physical Design,
{ISPD} 2009, San Diego, California, USA, March 29 - April 1, 2009},
pages = {149--150},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1514932.1514965},
doi = {10.1145/1514932.1514965},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/SzeRNA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PapaLMSLNAM08,
author = {David A. Papa and
Tao Luo and
Michael D. Moffitt and
Chin Ngai Sze and
Zhuo Li and
Gi{-}Joon Nam and
Charles J. Alpert and
Igor L. Markov},
title = {{RUMBLE:} An Incremental Timing-Driven Physical-Synthesis Optimization
Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {12},
pages = {2156--2168},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.2006155},
doi = {10.1109/TCAD.2008.2006155},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PapaLMSLNAM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LuoPLSAP08,
author = {Tao Luo and
David A. Papa and
Zhuo Li and
Chin Ngai Sze and
Charles J. Alpert and
David Z. Pan},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {Pyramids: an efficient computational geometry-based approach for timing-driven
placement},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {204--211},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681575},
doi = {10.1109/ICCAD.2008.4681575},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LuoPLSAP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/PapaLMSLNAM08,
author = {David A. Papa and
Tao Luo and
Michael D. Moffitt and
Chin Ngai Sze and
Zhuo Li and
Gi{-}Joon Nam and
Charles J. Alpert and
Igor L. Markov},
editor = {David Z. Pan and
Gi{-}Joon Nam},
title = {{RUMBLE:} an incremental, timing-driven, physical-synthesis optimization
algorithm},
booktitle = {Proceedings of the 2008 International Symposium on Physical Design,
{ISPD} 2008, Portland, Oregon, USA, April 13-16, 2008},
pages = {2--9},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353629.1353633},
doi = {10.1145/1353629.1353633},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/PapaLMSLNAM08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/NamSY08,
author = {Gi{-}Joon Nam and
Cliff C. N. Sze and
Mehmet Can Yildiz},
editor = {David Z. Pan and
Gi{-}Joon Nam},
title = {The {ISPD} global routing benchmark suite},
booktitle = {Proceedings of the 2008 International Symposium on Physical Design,
{ISPD} 2008, Portland, Oregon, USA, April 13-16, 2008},
pages = {156--159},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1353629.1353663},
doi = {10.1145/1353629.1353663},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/NamSY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/HuRS08,
author = {Jiang Hu and
Gabriel Robins and
Cliff C. N. Sze},
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Timing-Driven Interconnect Synthesis},
booktitle = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481.ch25},
doi = {10.1201/9781420013481.CH25},
timestamp = {Mon, 26 Oct 2020 09:04:39 +0100},
biburl = {https://dblp.org/rec/reference/crc/HuRS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/crc/HuS08,
author = {Jiang Hu and
Cliff C. N. Sze},
editor = {Charles J. Alpert and
Dinesh P. Mehta and
Sachin S. Sapatnekar},
title = {Buffering in the Layout Environment},
booktitle = {Handbook of Algorithms for Physical Design Automation},
publisher = {Auerbach Publications},
year = {2008},
url = {https://doi.org/10.1201/9781420013481.ch28},
doi = {10.1201/9781420013481.CH28},
timestamp = {Wed, 12 Jul 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/reference/crc/HuS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Sze07,
author = {Chin Ngai Sze},
title = {Algorithms for the scaling toward nanometer {VLSI} physical synthesis},
school = {Texas A{\&}M University, College Station, {USA}},
year = {2007},
url = {https://hdl.handle.net/1969.1/4922},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Sze07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/AlpertK0NQRSVY07,
author = {Charles J. Alpert and
Shrirang K. Karandikar and
Zhuo Li and
Gi{-}Joon Nam and
Stephen T. Quay and
Haoxing Ren and
Cliff C. N. Sze and
Paul G. Villarrubia and
Mehmet Can Yildiz},
title = {Techniques for Fast Physical Synthesis},
journal = {Proc. {IEEE}},
volume = {95},
number = {3},
pages = {573--599},
year = {2007},
url = {https://doi.org/10.1109/JPROC.2006.890096},
doi = {10.1109/JPROC.2006.890096},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/AlpertK0NQRSVY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SzeAHS07,
author = {Chin Ngai Sze and
Charles J. Alpert and
Jiang Hu and
Weiping Shi},
title = {Path-Based Buffer Insertion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {7},
pages = {1346--1355},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.888281},
doi = {10.1109/TCAD.2006.888281},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SzeAHS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuAHKLSS07,
author = {Shiyan Hu and
Charles J. Alpert and
Jiang Hu and
Shrirang K. Karandikar and
Zhuo Li and
Weiping Shi and
Chin Ngai Sze},
title = {Fast Algorithms for Slew-Constrained Minimum Cost Buffering},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {11},
pages = {2009--2022},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2007.906477},
doi = {10.1109/TCAD.2007.906477},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuAHKLSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/slip/AlpertKLNQRSVY07,
author = {Charles J. Alpert and
Shrirang K. Karandikar and
Zhuo Li and
Gi{-}Joon Nam and
Stephen T. Quay and
Haoxing Ren and
Cliff C. N. Sze and
Paul G. Villarrubia and
Mehmet Can Yildiz},
editor = {Andrew A. Kennings and
Ion I. Mandoiu},
title = {The nuts and bolts of physical synthesis},
booktitle = {The Ninth International Workshop on System-Level Interconnect Prediction
{(SLIP} 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings},
pages = {89--94},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1231956.1231975},
doi = {10.1145/1231956.1231975},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/slip/AlpertKLNQRSVY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertHSS06,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Cliff C. N. Sze},
title = {Accurate estimation of global buffer delay within a floorplan},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {25},
number = {6},
pages = {1140--1145},
year = {2006},
url = {https://doi.org/10.1109/TCAD.2005.855889},
doi = {10.1109/TCAD.2005.855889},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertHSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HuAHKLSS06,
author = {Shiyan Hu and
Charles J. Alpert and
Jiang Hu and
Shrirang K. Karandikar and
Zhuo Li and
Weiping Shi and
Cliff C. N. Sze},
editor = {Ellen Sentovich},
title = {Fast algorithms for slew constrained minimum cost buffering},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {308--313},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1146990},
doi = {10.1145/1146909.1146990},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HuAHKLSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AlpertKSW06,
author = {Charles J. Alpert and
Andrew B. Kahng and
Cliff C. N. Sze and
Qinke Wang},
editor = {Ellen Sentovich},
title = {Timing-driven Steiner trees are (practically) free},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {389--392},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1147012},
doi = {10.1145/1146909.1147012},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AlpertKSW06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/VenkataramanHLS06,
author = {Ganesh Venkataraman and
Jiang Hu and
Frank Liu and
Cliff C. N. Sze},
editor = {Georges G. E. Gielen},
title = {Integrated placement and skew optimization for rotary clocking},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {756--761},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244115},
doi = {10.1109/DATE.2006.244115},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/VenkataramanHLS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LuSHZCHH05,
author = {Yongqiang Lu and
Chin Ngai Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
title = {Navigating Register Placement for Low Power Clock Network Design},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3405--3411},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3405},
doi = {10.1093/IETFEC/E88-A.12.3405},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicet/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiSAHS05,
author = {Zhuo Li and
Cliff C. N. Sze and
Charles J. Alpert and
Jiang Hu and
Weiping Shi},
editor = {Tingao Tang},
title = {Making fast buffer insertion even faster via approximation techniques},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {13--18},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120733},
doi = {10.1145/1120725.1120733},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LiSAHS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LuSHZCHH05,
author = {Yongqiang Lu and
Cliff C. N. Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
editor = {Tingao Tang},
title = {Register placement for low power clock network},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {588--593},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120971},
doi = {10.1145/1120725.1120971},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/VenkataramanSH05,
author = {Ganesh Venkataraman and
Cliff C. N. Sze and
Jiang Hu},
editor = {Tingao Tang},
title = {Skew scheduling and clock routing for improved tolerance to process
variations},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {594--599},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120972},
doi = {10.1145/1120725.1120972},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/VenkataramanSH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LuSHZCHH05,
author = {Yongqiang Lu and
Cliff C. N. Sze and
Xianlong Hong and
Qiang Zhou and
Yici Cai and
Liang Huang and
Jiang Hu},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Navigating registers in placement for clock network minimization},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {176--181},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065628},
doi = {10.1145/1065579.1065628},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LuSHZCHH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SzeAHS05,
author = {Cliff C. N. Sze and
Charles J. Alpert and
Jiang Hu and
Weiping Shi},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Path based buffer insertion},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {509--514},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065711},
doi = {10.1145/1065579.1065711},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SzeAHS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpertGHHQS04,
author = {Charles J. Alpert and
Gopal Gandham and
Milos Hrkic and
Jiang Hu and
Stephen T. Quay and
Cliff C. N. Sze},
title = {Porosity-aware buffered Steiner tree construction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {4},
pages = {517--526},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.825864},
doi = {10.1109/TCAD.2004.825864},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpertGHHQS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SzeWW04,
author = {Cliff C. N. Sze and
Ting{-}Chi Wang and
Li{-}C. Wang},
title = {Multilevel circuit clustering for delay minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {7},
pages = {1073--1085},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.829817},
doi = {10.1109/TCAD.2004.829817},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SzeWW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SzeHA04,
author = {Cliff C. N. Sze and
Jiang Hu and
Charles J. Alpert},
editor = {Masaharu Imai},
title = {A place and route aware buffered Steiner tree construction},
booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
Electronic Design and Solution Fair 2004, Yokohama, Japan, January
27-30, 2004},
pages = {355--360},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.29},
doi = {10.1109/ASPDAC.2004.29},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SzeHA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AlpertHSS04,
author = {Charles J. Alpert and
Jiang Hu and
Sachin S. Sapatnekar and
Cliff C. N. Sze},
title = {Accurate estimation of global buffer delay within a floorplan},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {706--711},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382667},
doi = {10.1109/ICCAD.2004.1382667},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AlpertHSS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SzeW03,
author = {Cliff C. N. Sze and
Ting{-}Chi Wang},
title = {Optimal circuit clustering for delay minimization under a more general
delay model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {22},
number = {5},
pages = {646--651},
year = {2003},
url = {https://doi.org/10.1109/TCAD.2003.810746},
doi = {10.1109/TCAD.2003.810746},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SzeW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SzeW03,
author = {Chin Ngai Sze and
Ting{-}Chi Wang},
editor = {Hiroto Yasuura},
title = {Performance-driven multi-level clustering for combinational circuits},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {729--740},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119935},
doi = {10.1145/1119772.1119935},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SzeW03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/SzeLWB02,
author = {Chin Ngai Sze and
Wangning Long and
Yu{-}Liang Wu and
Jinian Bian},
title = {Accelerating Logic Rewiring Using Implication Analysis Tree},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {85-A},
number = {12},
pages = {2725--2736},
year = {2002},
url = {http://search.ieice.org/bin/summary.php?id=e85-a\_12\_2725},
timestamp = {Fri, 01 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/SzeLWB02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SzeW02,
author = {Cliff C. N. Sze and
Ting{-}Chi Wang},
title = {Optimal circuit clustering with variable interconnect delay},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {707--710},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1010555},
doi = {10.1109/ISCAS.2002.1010555},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SzeW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwls/SzeW02,
author = {Cliff C. N. Sze and
Ting{-}Chi Wang},
title = {Multi-Level Circuit Clustering for Delay Minimization},
booktitle = {11th {IEEE/ACM} International Workshop on Logic {\&} Synthesis,
{IWLS} 2002, June 4-7, 2002, New Orleans, Louisiana, {USA}},
pages = {227--232},
year = {2002},
timestamp = {Sun, 04 Aug 2019 18:01:44 +0200},
biburl = {https://dblp.org/rec/conf/iwls/SzeW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SzeW01,
author = {Chin Ngai Sze and
Yu{-}Liang Wu},
editor = {Satoshi Goto},
title = {Improved alternative wiring scheme applying dominator relationship},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {473--478},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370515},
doi = {10.1145/370155.370515},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SzeW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/WuSCF00,
author = {Yu{-}Liang Wu and
Chin Ngai Sze and
Chak{-}Chung Cheung and
Hongbing Fan},
title = {On improved graph-based alternative wiring scheme for multi-level
logic optimization},
booktitle = {Proceedings of the 2000 7th {IEEE} International Conference on Electronics,
Circuits and Systems, {ICECS} 2000, Jounieh, Lebanon, December 17-20,
2000},
pages = {654--657},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ICECS.2000.912962},
doi = {10.1109/ICECS.2000.912962},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/WuSCF00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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