BibTeX records: Chetan Kumar V.

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@inproceedings{DBLP:conf/dsd/VPAVMS11,
  author       = {Chetan Kumar V. and
                  P. Sai Phaneendra and
                  Syed Ershad Ahmed and
                  Sreehari Veeramachaneni and
                  N. Moorthy Muthukrishnan and
                  M. B. Srinivas},
  title        = {A Unified Architecture for {BCD} and Binary Adder/Subtractor},
  booktitle    = {14th Euromicro Conference on Digital System Design, Architectures,
                  Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,
                  Finland},
  pages        = {426--429},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/DSD.2011.58},
  doi          = {10.1109/DSD.2011.58},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dsd/VPAVMS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ised/VPAVMS11,
  author       = {Chetan Kumar V. and
                  P. Sai Phaneendra and
                  Syed Ershad Ahmed and
                  Sreehari Veeramachaneni and
                  N. Moorthy Muthukrishnan and
                  M. B. Srinivas},
  title        = {A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with
                  Improved Decision Block},
  booktitle    = {International Symposium on Electronic System Design, {ISED} 2011,
                  Kochi, Kerala, India, December 19-21, 2011},
  pages        = {100--105},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISED.2011.52},
  doi          = {10.1109/ISED.2011.52},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ised/VPAVMS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isvlsi/VPAVMS11,
  author       = {Chetan Kumar V. and
                  Sai Phaneendra P. and
                  Syed Ershad Ahmed and
                  Sreehari Veeramachaneni and
                  N. Moorthy Muthukrishnan and
                  M. B. Srinivas},
  title        = {A Prefix Based Reconfigurable Adder},
  booktitle    = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
                  July 2011, Chennai, India},
  pages        = {349--350},
  publisher    = {{IEEE} Computer Society},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISVLSI.2011.69},
  doi          = {10.1109/ISVLSI.2011.69},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isvlsi/VPAVMS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}