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ORCIDBibTeX records: M. H. Vasantha
@article{DBLP:journals/access/ShreeharshaKVN24,
author = {K. G. Shreeharsha and
Siddharth R. K. and
M. H. Vasantha and
Kumar Y. B. Nithin},
title = {An Error Bound Particle Swarm Optimization for Analog Circuit Sizing},
journal = {{IEEE} Access},
volume = {12},
pages = {50126--50136},
year = {2024},
url = {https://doi.org/10.1109/ACCESS.2024.3385491},
doi = {10.1109/ACCESS.2024.3385491},
timestamp = {Tue, 16 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/ShreeharshaKVN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/ShreeharshaKVK23,
author = {K. G. Shreeharsha and
Siddharth R. K. and
M. H. Vasantha and
Y. B. Nithin Kumar},
title = {Partition Bound Random Number-Based Particle Swarm Optimization for
Analog Circuit Sizing},
journal = {{IEEE} Access},
volume = {11},
pages = {123577--123588},
year = {2023},
url = {https://doi.org/10.1109/ACCESS.2023.3329698},
doi = {10.1109/ACCESS.2023.3329698},
timestamp = {Tue, 28 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/ShreeharshaKVK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/BalajiKNKVB23,
author = {R. D. Balaji and
Siddharth R. K. and
Sanmitra Bharat Naik and
Y. B. Nithin Kumar and
M. H. Vasantha and
Edoardo Bonizzoni},
title = {A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter
in 65-nm {CMOS}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181677},
doi = {10.1109/ISCAS46773.2023.10181677},
timestamp = {Mon, 31 Jul 2023 09:04:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/BalajiKNKVB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/HalliyavarKHBR23,
author = {Darshan Halliyavar and
Siddharth R. K. and
Vasantha M. H. and
Nithin Kumar Y. B. and
Sithara Raveendran},
title = {Approximate Three-Operand Binary Adder for Error-Resilient Applications},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2023,
Ahmedabad, India, December 18-20, 2023},
pages = {287--291},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/iSES58672.2023.00065},
doi = {10.1109/ISES58672.2023.00065},
timestamp = {Tue, 02 Apr 2024 12:53:25 +0200},
biburl = {https://dblp.org/rec/conf/ises/HalliyavarKHBR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KadhaoKBHD23,
author = {Rupesh D. Kadhao and
Siddharth R. K. and
Nithin Kumar Y. B. and
Vasantha M. H. and
Devesh Dwivedi},
title = {A 2.5 GHz, 1-Kb {SRAM} with Auxiliary Circuit Assisted Sense Amplifier
in 65-nm {CMOS} Process},
booktitle = {36th International Conference on {VLSI} Design and 2023 22nd International
Conference on Embedded Systems, {VLSID} 2023, Hyderabad, India, January
8-12, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VLSID57277.2023.00036},
doi = {10.1109/VLSID57277.2023.00036},
timestamp = {Sat, 22 Apr 2023 17:02:07 +0200},
biburl = {https://dblp.org/rec/conf/vlsid/KadhaoKBHD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/RaveendranEKV22,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Y. B. Nithin Kumar and
M. H. Vasantha},
title = {On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible
Logic},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {3428--3432},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937995},
doi = {10.1109/ISCAS48785.2022.9937995},
timestamp = {Thu, 17 Nov 2022 15:59:17 +0100},
biburl = {https://dblp.org/rec/conf/iscas/RaveendranEKV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/RaveendranEBV21,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Nithin Kumar Yernad Balachandra and
M. H. Vasantha},
title = {Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic},
journal = {{IEEE} Access},
volume = {9},
pages = {108119--108130},
year = {2021},
url = {https://doi.org/10.1109/ACCESS.2021.3100892},
doi = {10.1109/ACCESS.2021.3100892},
timestamp = {Thu, 12 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/access/RaveendranEBV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/VeerendranathSV21,
author = {P. S. Veerendranath and
Vivek Sharma and
M. H. Vasantha and
Y. B. Nithin Kumar},
title = {{\textdollar}{\textbackslash}pm {\textbackslash}, 0.5{\textdollar}
V, 254 {\textdollar}{\textbackslash}upmu {\textdollar}W Second-Order
Tunable Biquad Low-Pass Filter with 7.3 fJ {FOM} Using a Novel Low-Voltage
Fully Balanced Current-Mode Circuit},
journal = {Circuits Syst. Signal Process.},
volume = {40},
number = {5},
pages = {2114--2134},
year = {2021},
url = {https://doi.org/10.1007/s00034-020-01575-8},
doi = {10.1007/S00034-020-01575-8},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cssp/VeerendranathSV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ReddyVKGD21,
author = {Karri Manikantta Reddy and
M. H. Vasantha and
Nithin Y. B. Kumar and
Ch. Keshava Gopal and
Devesh Dwivedi},
title = {Quantization aware approximate multiplier and hardware accelerator
for edge computing of deep learning applications},
journal = {Integr.},
volume = {81},
pages = {268--279},
year = {2021},
url = {https://doi.org/10.1016/j.vlsi.2021.08.001},
doi = {10.1016/J.VLSI.2021.08.001},
timestamp = {Wed, 03 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ReddyVKGD21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/VeerendranathSV21,
author = {P. S. Veerendranath and
Vivek Sharma and
M. H. Vasantha and
Y. B. Nithin Kumar},
title = {A Novel Complex Filter Design With Dual Feedback for High Frequency
Wireless Receiver Applications},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {68},
number = {6},
pages = {1748--1752},
year = {2021},
url = {https://doi.org/10.1109/TCSII.2020.3031658},
doi = {10.1109/TCSII.2020.3031658},
timestamp = {Wed, 15 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasII/VeerendranathSV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Guruprakashkumar21,
author = {Peta Guruprakashkumar and
Siddharth R. K. and
Nithin Kumar Y. B. and
Vasantha M. H. and
Edoardo Bonizzoni},
title = {A 1-V, 5-Bit, 180-{\(\mathrm{\mu}\)}W, Differential Pulse Position
Modulation {ADC} in 65-nm {CMOS} Process},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401108},
doi = {10.1109/ISCAS51556.2021.9401108},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Guruprakashkumar21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/ShreeharshaKVK21,
author = {K. G. Shreeharsha and
Charudatta Korde and
M. H. Vasantha and
Y. B. Nithin Kumar},
title = {Training of Generative Adversarial Networks using Particle Swarm Optimization
Algorithm},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2021,
Jaipur, India, December 18-22, 2021},
pages = {127--130},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/iSES52644.2021.00038},
doi = {10.1109/ISES52644.2021.00038},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/ShreeharshaKVK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KumarKBV21,
author = {Shiv Chandra Kumar and
Siddharth R. K. and
Nithin Kumar Y. B. and
M. H. Vasantha},
title = {A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented {DAC} for Video
Applications},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2021, Tampa,
FL, USA, July 7-9, 2021},
pages = {19--24},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISVLSI51109.2021.00015},
doi = {10.1109/ISVLSI51109.2021.00015},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/KumarKBV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/NaikKCNVK21,
author = {Sanmitra Bharat Naik and
Siddharth R. K. and
Anirban Chatterjee and
Kumar Y. B. Nithin and
M. H. Vasantha and
Ramnath Kini},
title = {A 1 {V} Double-Balanced Mixer for 2.4-2.5 GHz {ISM} Band Applications},
booktitle = {34th International Conference on {VLSI} Design and 20th International
Conference on Embedded Systems, {VLSID} 2021, Guwahati, India, February
20-24, 2021},
pages = {252--257},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VLSID51830.2021.00048},
doi = {10.1109/VLSID51830.2021.00048},
timestamp = {Mon, 14 Nov 2022 15:28:08 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/NaikKCNVK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/access/RaveendranEKV20,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {An Approximate Low-Power Lifting Scheme Using Reversible Logic},
journal = {{IEEE} Access},
volume = {8},
pages = {183367--183377},
year = {2020},
url = {https://doi.org/10.1109/ACCESS.2020.3029149},
doi = {10.1109/ACCESS.2020.3029149},
timestamp = {Tue, 01 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/access/RaveendranEKV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/KalaCBHB20,
author = {Siddharth Rajkumar Kala and
Sushma Chandaka and
Nithin Kumar Yernad Balachandra and
Vasantha Moodabettu Harishchandra and
Edoardo Bonizzoni},
title = {6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator
in 65 nm {CMOS} process},
journal = {{IET} Circuits Devices Syst.},
volume = {14},
number = {3},
pages = {340--346},
year = {2020},
url = {https://doi.org/10.1049/iet-cds.2019.0421},
doi = {10.1049/IET-CDS.2019.0421},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/KalaCBHB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/SharmaBH20,
author = {Vivek Sharma and
Nithin Kumar Y. B. and
Vasantha M. H.},
title = {{IET} Circuits, Devices {\&} Systems},
journal = {{IET} Circuits Devices Syst.},
volume = {14},
number = {6},
pages = {881--891},
year = {2020},
url = {https://doi.org/10.1049/iet-cds.2019.0414},
doi = {10.1049/IET-CDS.2019.0414},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/SharmaBH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-ipr/RaveendranEBH20,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Nithin Kumar Yernad Balachandra and
Vasantha Moodabettu Harishchandra},
title = {Design and implementation of image kernels using reversible logic
gates},
journal = {{IET} Image Process.},
volume = {14},
number = {16},
pages = {4110--4121},
year = {2020},
url = {https://doi.org/10.1049/iet-ipr.2019.1681},
doi = {10.1049/IET-IPR.2019.1681},
timestamp = {Thu, 18 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-ipr/RaveendranEBH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/BoroRKV20,
author = {Bipul Boro and
Karri Manikantta Reddy and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {Approximate radix-8 Booth multiplier for low power and high speed
applications},
journal = {Microelectron. J.},
volume = {101},
pages = {104816},
year = {2020},
url = {https://doi.org/10.1016/j.mejo.2020.104816},
doi = {10.1016/J.MEJO.2020.104816},
timestamp = {Sun, 17 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/BoroRKV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sncs/KKV20,
author = {Siddharth R. K. and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {Power Saving Scheme for Process Corner Calibrated Standard Cell Based
Flash {ADC} in Wireless Surveillance Applications},
journal = {{SN} Comput. Sci.},
volume = {1},
number = {6},
pages = {310},
year = {2020},
url = {https://doi.org/10.1007/s42979-020-00328-3},
doi = {10.1007/S42979-020-00328-3},
timestamp = {Tue, 09 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sncs/KKV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KSKVB20,
author = {Siddharth R. K. and
Y. Jaya Satyanarayana and
Nithin Y. B. Kumar and
M. H. Vasantha and
Edoardo Bonizzoni},
title = {A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications},
journal = {{IEEE} Trans. Circuits Syst.},
volume = {67-II},
number = {12},
pages = {2918--2922},
year = {2020},
url = {https://doi.org/10.1109/TCSII.2020.2993064},
doi = {10.1109/TCSII.2020.2993064},
timestamp = {Tue, 09 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/KSKVB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ReddyVKD20,
author = {Karri Manikantta Reddy and
M. H. Vasantha and
Nithin Y. B. Kumar and
Devesh Dwivedi},
title = {Design of Approximate Booth Squarer for Error-Tolerant Computing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {5},
pages = {1230--1241},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2976131},
doi = {10.1109/TVLSI.2020.2976131},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ReddyVKD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/KumarKKV20,
author = {Nitish Kumar and
Siddharth R. K. and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {A 1 V, 39 {\(\mu\)} W, 5-bit Multi-Level Comparator based Flash {ADC}},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2020
(Formerly iNiS), Chennai, India, December 14-16, 2020},
pages = {167--170},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/iSES50453.2020.00045},
doi = {10.1109/ISES50453.2020.00045},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/KumarKKV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/ShahaneKNH20,
author = {Tejas J. Shahane and
Siddharth R. K. and
Kumar Y. B. Nithin and
Vasantha M. H.},
title = {A 1.8 V, Mode-Configurable Hybrid Smart {ADC}},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2020
(Formerly iNiS), Chennai, India, December 14-16, 2020},
pages = {216--220},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/iSES50453.2020.00056},
doi = {10.1109/ISES50453.2020.00056},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/ShahaneKNH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/NaikKCBVK20,
author = {Sanmitra Bharat Naik and
Siddharth R. K. and
Anirban Chatterjee and
Nithin Kumar Y. B. and
M. H. Vasantha and
Ramnath Kini},
title = {A 1.8 {V} Quadrature Phase {LC} Oscillator for 5G Applications},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2020
(Formerly iNiS), Chennai, India, December 14-16, 2020},
pages = {277--280},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/iSES50453.2020.00068},
doi = {10.1109/ISES50453.2020.00068},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ises/NaikKCBVK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/DoharKHB20,
author = {Suraj Dohar and
Siddharth R. K. and
Vasantha M. H. and
Nithin Kumar Y. B.},
title = {A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace
Applications},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {48--53},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00019},
doi = {10.1109/ISVLSI49217.2020.00019},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/DoharKHB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/RaveendranEBV20,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Nithin Kumar Y. B. and
M. H. Vasantha},
title = {Reversible Logic Implementation of Image Denoising for Grayscale Images},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {138--141},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184481},
doi = {10.1109/MWSCAS48704.2020.9184481},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/RaveendranEBV20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/NaikKCBHK20,
author = {Sanmitra Bharat Naik and
Siddharth R. K. and
Anirban Chatterjee and
Nithin Kumar Y. B. and
Vasantha M. H. and
Ramnath Kini},
title = {A Wideband 12 Phase Ring Oscillator for 5G Applications},
booktitle = {63rd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2020, Springfield, MA, USA, August 9-12, 2020},
pages = {885--888},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184463},
doi = {10.1109/MWSCAS48704.2020.9184463},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/NaikKCBHK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/SHL19,
author = {S. Rekha and
Vasantha Moodabettu Harishchandra and
Tonse Laxminidhi},
title = {Ultra-low voltage, power efficient continuous-time filters in 180
nm {CMOS} technology},
journal = {{IET} Circuits Devices Syst.},
volume = {13},
number = {7},
pages = {988--997},
year = {2019},
url = {https://doi.org/10.1049/iet-cds.2018.5485},
doi = {10.1049/IET-CDS.2018.5485},
timestamp = {Tue, 25 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/SHL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/RSBH19,
author = {Pradeep R. and
Siddharth R. K. and
Nithin Kumar Yernad Balachandra and
Vasantha Moodabettu Harishchandra},
title = {Process Corner Calibration for Standard Cell Based Flash {ADC}},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2019
(Formerly iNiS), Rourkela, India, December 16-18, 2019},
pages = {195--200},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/iSES47678.2019.00051},
doi = {10.1109/ISES47678.2019.00051},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/RSBH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/ESSVB19,
author = {Rahul E. and
Siddharth R. K. and
Vivek Sharma and
M. H. Vasantha and
Nithin Kumar Yernad Balachandra},
title = {Two-Step Flash {ADC} Using Standard Cell Based Flash ADCs},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2019
(Formerly iNiS), Rourkela, India, December 16-18, 2019},
pages = {292--295},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/iSES47678.2019.00072},
doi = {10.1109/ISES47678.2019.00072},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/ESSVB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RSKV19,
author = {Sunil R. and
Siddharth R. K. and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {An Asynchronous Analog to Digital Converter for Video Camera Applications},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {175--180},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00040},
doi = {10.1109/ISVLSI.2019.00040},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RSKV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VernekarBH19,
author = {Prasad Vernekar and
Nithin Kumar Yernad Balachandra and
Vasantha Moodabettu Harishchandra},
title = {Self Timed {SRAM} Array with Enhanced low Voltage Read and Write Capability},
booktitle = {2019 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2019,
Miami, FL, USA, July 15-17, 2019},
pages = {627--631},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISVLSI.2019.00117},
doi = {10.1109/ISVLSI.2019.00117},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VernekarBH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/PujarRPHB19,
author = {Jagadeesh Pujar and
Sithara Raveendran and
Trilochan Panigrahi and
Vasantha M. H. and
Nithin Kumar Y. B.},
editor = {Hoi Lee and
Randall L. Geiger},
title = {Design and Analysis of Energy Efficient Reversible Logic based Full
Adder},
booktitle = {62nd {IEEE} International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2019, Dallas, TX, USA, August 4-7, 2019},
pages = {339--342},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MWSCAS.2019.8884882},
doi = {10.1109/MWSCAS.2019.8884882},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/PujarRPHB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tencon/VeerendranathSK19,
author = {P. S. Veerendranath and
Vivek Sharma and
Nithin Y. B. Kumar and
M. H. Vasantha and
Edoardo Bonizzoni},
title = {Current Conveyor based Novel Gyrator filter for Biomedical Sensor
Applications},
booktitle = {{TENCON} 2019 - 2019 {IEEE} Region 10 Conference (TENCON), Kochi,
India, October 17-20, 2019},
pages = {658--661},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/TENCON.2019.8929308},
doi = {10.1109/TENCON.2019.8929308},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/tencon/VeerendranathSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jnca/BeechuHB18,
author = {Naresh Kumar Reddy Beechu and
Vasantha Moodabettu Harishchandra and
Nithin Kumar Yernad Balachandra},
title = {An energy-efficient fault-aware core mapping in mesh-based network
on chip systems},
journal = {J. Netw. Comput. Appl.},
volume = {105},
pages = {79--87},
year = {2018},
url = {https://doi.org/10.1016/j.jnca.2017.12.019},
doi = {10.1016/J.JNCA.2017.12.019},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jnca/BeechuHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/telsys/BeechuHB18,
author = {Naresh Kumar Reddy Beechu and
Vasantha Moodabettu Harishchandra and
Nithin Kumar Yernad Balachandra},
title = {Hardware implementation of fault tolerance NoC core mapping},
journal = {Telecommun. Syst.},
volume = {68},
number = {4},
pages = {621--630},
year = {2018},
url = {https://doi.org/10.1007/s11235-017-0412-2},
doi = {10.1007/S11235-017-0412-2},
timestamp = {Thu, 13 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/telsys/BeechuHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/wpc/BeechuHB18,
author = {Naresh Kumar Reddy Beechu and
Vasantha Moodabettu Harishchandra and
Nithin Kumar Yernad Balachandra},
title = {Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures},
journal = {Wirel. Pers. Commun.},
volume = {100},
number = {2},
pages = {213--225},
year = {2018},
url = {https://doi.org/10.1007/s11277-017-5061-y},
doi = {10.1007/S11277-017-5061-Y},
timestamp = {Thu, 20 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/wpc/BeechuHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ieeesensors/KalekarVVKB18,
author = {Purnima Kalekar and
Prasad Vernekar and
M. H. Vasantha and
Y. B. Nithin Kumar and
Edoardo Bonizzoni},
title = {A 0.5 {V} Low Power {DTMOS} {OTA-C} Filter for {ECG} Sensing Applications},
booktitle = {2018 {IEEE} SENSORS, New Delhi, India, October 28-31, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICSENS.2018.8589852},
doi = {10.1109/ICSENS.2018.8589852},
timestamp = {Sun, 12 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ieeesensors/KalekarVVKB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SiddharthNVB18,
author = {Siddharth R. K. and
Kumar Y. B. Nithin and
M. H. Vasantha and
Edoardo Bonizzoni},
title = {A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor
Applications},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2018,
27-30 May 2018, Florence, Italy},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISCAS.2018.8351368},
doi = {10.1109/ISCAS.2018.8351368},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/SiddharthNVB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/BarveRKPKV18,
author = {Sampada Barve and
Sithara Raveendran and
Charudatta Korde and
Trilochan Panigrahi and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {{FPGA} Implementation of Square and Cube Architecture Using Vedic
Mathematics},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018
(Formerly iNiS), Hyderabad, India, December 17-19, 2018},
pages = {6--10},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/iSES.2018.00012},
doi = {10.1109/ISES.2018.00012},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/BarveRKPKV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/KambleSPVK18,
author = {Chetan Kamble and
Siddharth R. K. and
Shivnarayan Patidar and
M. H. Vasantha and
Nithin Y. B. Kumar},
title = {Design of Area-Power-Delay Efficient Square Root Carry Select Adder},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018
(Formerly iNiS), Hyderabad, India, December 17-19, 2018},
pages = {80--85},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/iSES.2018.00026},
doi = {10.1109/ISES.2018.00026},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/KambleSPVK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/PandeyRYKV18,
author = {Anirudha Pandey and
Karri Manikantta Reddy and
Praveen Yadav and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {Design and Analysis of Approximate Multipliers for Error-Tolerant
Applications},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018
(Formerly iNiS), Hyderabad, India, December 17-19, 2018},
pages = {94--97},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/iSES.2018.00029},
doi = {10.1109/ISES.2018.00029},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/PandeyRYKV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SiddharthRKVB18,
author = {Siddharth R. K. and
Sunil R. and
Nithin Y. B. Kumar and
M. H. Vasantha and
Edoardo Bonizzoni},
title = {An Asynchronous Analog to Digital Converter for Surveillance Camera
Applications},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {164--169},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00039},
doi = {10.1109/ISVLSI.2018.00039},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SiddharthRKVB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AntoTNV18,
author = {Donel Anto and
Abhijeet D. Taralkar and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {Performance Enhancement of Split Length Compensated Operational Amplifiers},
booktitle = {2018 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2018,
Hong Kong, China, July 8-11, 2018},
pages = {608--613},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISVLSI.2018.00116},
doi = {10.1109/ISVLSI.2018.00116},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AntoTNV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ReddyVND18,
author = {Karri Manikantta Reddy and
M. H. Vasantha and
Kumar Y. B. Nithin and
Devesh Dwivedi},
title = {Design of Approximate Dividers for Error Tolerant Applications},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {496--499},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8623909},
doi = {10.1109/MWSCAS.2018.8623909},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/ReddyVND18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/YadavPKPVK18,
author = {Praveen Yadav and
Anirudha Pandey and
Karri Manikantta Reddy and
K. J. Ravi Prasad and
M. H. Vasantha and
Nithin Y. B. Kumar},
title = {Low Power Approximate Multipliers With Truncated Carry Propagation
for LSBs},
booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
pages = {500--503},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/MWSCAS.2018.8624067},
doi = {10.1109/MWSCAS.2018.8624067},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mwscas/YadavPKPVK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tencon/ShashidharSPKV18,
author = {Dhavala Shashidhar and
Vivek Sharma and
G. R. Prashanth and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {Characterization of a Novel Low Leakage Power-Efficient Asymmetric
7T {SRAM} Cell},
booktitle = {{TENCON} 2018 - 2018 {IEEE} Region 10 Conference, Jeju, South Korea,
October 28-31, 2018},
pages = {1768--1773},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/TENCON.2018.8650534},
doi = {10.1109/TENCON.2018.8650534},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/tencon/ShashidharSPKV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tencon/RaveendranEKV18,
author = {Sithara Raveendran and
Pranose J. Edavoor and
Nithin Y. B. Kumar and
M. H. Vasantha},
title = {Design and Implementation of Reversible Logic based {RGB} to Gray
scale Color Space Converter},
booktitle = {{TENCON} 2018 - 2018 {IEEE} Region 10 Conference, Jeju, South Korea,
October 28-31, 2018},
pages = {1813--1817},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/TENCON.2018.8650243},
doi = {10.1109/TENCON.2018.8650243},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/tencon/RaveendranEKV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeerendranathVK18,
author = {P. S. Veerendranath and
M. H. Vasantha and
Kumar Y. B. Nithin and
Edoardo Bonizzoni},
title = {A Novel Low Power {G} m-C Continuous-Time Analog Filter with Wide
Tuning Range},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {214--219},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.65},
doi = {10.1109/VLSID.2018.65},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeerendranathVK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/BecchuHB17,
author = {Naresh Kumar Reddy Becchu and
Vasantha Moodabettu Harishchandra and
Nithin Kumar Yernad Balachandra},
title = {System level fault-tolerance core mapping and FPGA-based verification
of NoC},
journal = {Microelectron. J.},
volume = {70},
pages = {16--26},
year = {2017},
url = {https://doi.org/10.1016/j.mejo.2017.09.010},
doi = {10.1016/J.MEJO.2017.09.010},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/BecchuHB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/suscom/BeechuHB17,
author = {Naresh Kumar Reddy Beechu and
Vasantha Moodabettu Harishchandra and
Nithin Kumar Yernad Balachandra},
title = {High-performance and energy-efficient fault-tolerance core mapping
in NoC},
journal = {Sustain. Comput. Informatics Syst.},
volume = {16},
pages = {1--10},
year = {2017},
url = {https://doi.org/10.1016/j.suscom.2017.08.004},
doi = {10.1016/J.SUSCOM.2017.08.004},
timestamp = {Tue, 25 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/suscom/BeechuHB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/DBH17,
author = {Anoop D and
Nithin Kumar Yernad Balachandra and
Vasantha Moodabettu Harishchandra},
title = {High Performance Sense Amplifier Based Flip Flop for Driver Applications},
booktitle = {{IEEE} International Symposium on Nanoelectronic and Information Systems,
iNIS 2017, Bhopal, India, December 18-20, 2017},
pages = {129--132},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.ieeecomputersociety.org/10.1109/iNIS.2017.35},
doi = {10.1109/INIS.2017.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/DBH17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KhalapureSNV17,
author = {Sumit Khalapure and
Siddharth R. K. and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {Design of 5-Bit Flash {ADC} Using Multiple Input Standard Cell Gates
for Large Input Swing},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {585--588},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.108},
doi = {10.1109/ISVLSI.2017.108},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/KhalapureSNV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RTVN17,
author = {Rakhi R. and
Abhijeet D. Taralkar and
M. H. Vasantha and
Kumar Y. B. Nithin},
title = {A 0.5 {V} Low Power {OTA-C} Low Pass Filter for {ECG} Detection},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {589--593},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.109},
doi = {10.1109/ISVLSI.2017.109},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RTVN17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MayurSNV17,
author = {S. M. Mayur and
Siddharth R. K. and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash {ADC}},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {600--603},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.111},
doi = {10.1109/ISVLSI.2017.111},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MayurSNV17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icccnt/EdavoorRVPNV16,
author = {Pranose J. Edavoor and
Sithara Raveendran and
Arjun T. V. and
Sumesh K. P. and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {{FPGA} realisation of {PSNR} and {BPP} driven Adaptive Compression
and Encryption Algorithm for {RGB} Images},
booktitle = {Proceedings of the 7th International Conference on Computing Communication
and Networking Technologies, {ICCCNT} 2016, Dallas, TX, USA, July
6-8, 2016},
pages = {35:1--35:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2967878.2967917},
doi = {10.1145/2967878.2967917},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icccnt/EdavoorRVPNV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/SaurabhKPV16,
author = {Saurabh B. Kaurati and
Nithin Y. B. Kumar and
Shivnarayan Patidar and
M. H. Vasantha},
title = {Design and Implementation of Tunable Bandpass Filter for Biomedical
Applications},
booktitle = {{IEEE} International Symposium on Nanoelectronic and Information Systems,
iNIS 2016, Gwalior, India, December 19-21, 2016},
pages = {43--46},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/iNIS.2016.021},
doi = {10.1109/INIS.2016.021},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/SaurabhKPV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AhishSVN16,
author = {S. Ahish and
Dheeraj Sharma and
M. H. Vasantha and
Kumar Y. B. Nithin},
title = {Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel
Field Effect Transistor},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {105--109},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.52},
doi = {10.1109/ISVLSI.2016.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AhishSVN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ReddyVN16,
author = {B. Naresh Kumar Reddy and
M. H. Vasantha and
Kumar Y. B. Nithin},
title = {A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using
Spare Core},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {146--151},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.80},
doi = {10.1109/ISVLSI.2016.80},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ReddyVN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MayurSNV16,
author = {S. M. Mayur and
Siddharth R. K. and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {Design of Low Power 5-Bit Hybrid Flash {ADC}},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {343--348},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.53},
doi = {10.1109/ISVLSI.2016.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MayurSNV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VenkatareddySNV16,
author = {A. Venkatareddy and
Sithara Raveendran and
Kumar Y. B. Nithin and
M. H. Vasantha},
title = {Characterization of a Novel Low Leakage Power and Area Efficient 7T
{SRAM} Cell},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {202--206},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.28},
doi = {10.1109/VLSID.2016.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VenkatareddySNV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ReddyNSV15,
author = {Karri Manikantta Reddy and
Kumar Y. B. Nithin and
Dheeraj Sharma and
M. H. Vasantha},
title = {Low power, high speed error tolerant multiplier using approximate
adders},
booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
Ahmedabad, India, June 26-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVDAT.2015.7208150},
doi = {10.1109/ISVDAT.2015.7208150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vdat/ReddyNSV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/HL12,
author = {Vasantha M. H. and
Tonse Laxminidhi},
title = {0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 {\(\mathrm{\mu}\)}m
{CMOS} Process},
booktitle = {International Symposium on Electronic System Design, ISEDs 2012, Kolkata,
India, December 19-22, 2012},
pages = {33--37},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISED.2012.46},
doi = {10.1109/ISED.2012.46},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/ised/HL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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