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ORCIDBibTeX records: Daniel Ziener
@inproceedings{DBLP:conf/arcs/AsgharRTBZ22,
author = {Ali Asghar and
Amanda Katherine Robillard and
Ilya Tuzov and
Andreas Becher and
Daniel Ziener},
editor = {Martin Schulz and
Carsten Trinitis and
Nikela Papadopoulou and
Thilo Pionteck},
title = {Using Look Up Table Content as Signatures to Identify {IP} Cores in
Modern FPGAs},
booktitle = {Architecture of Computing Systems - 35th International Conference,
{ARCS} 2022, Heilbronn, Germany, September 13-15, 2022, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {13642},
pages = {132--147},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-21867-5\_9},
doi = {10.1007/978-3-031-21867-5\_9},
timestamp = {Tue, 20 Dec 2022 09:38:33 +0100},
biburl = {https://dblp.org/rec/conf/arcs/AsgharRTBZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/AsgharHKZ21,
author = {Ali Asghar and
Benjamin Hettwer and
Emil Karimov and
Daniel Ziener},
editor = {Steven Derrien and
Frank Hannig and
Pedro C. Diniz and
Daniel Chillet},
title = {Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based
Reconfiguration},
booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications
- 17th International Symposium, {ARC} 2021, Virtual Event, June 29-30,
2021, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12700},
pages = {173--187},
publisher = {Springer},
year = {2021},
url = {https://doi.org/10.1007/978-3-030-79025-7\_12},
doi = {10.1007/978-3-030-79025-7\_12},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/AsgharHKZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/IrmakZA21,
author = {Hasan Irmak and
Daniel Ziener and
Nikolaos Alachiotis},
title = {Increasing Flexibility of FPGA-based {CNN} Accelerators with Dynamic
Partial Reconfiguration},
booktitle = {31st International Conference on Field-Programmable Logic and Applications,
{FPL} 2021, Dresden, Germany, August 30 - Sept. 3, 2021},
pages = {306--311},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/FPL53798.2021.00061},
doi = {10.1109/FPL53798.2021.00061},
timestamp = {Mon, 09 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/IrmakZA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/siu/IrmakAZ21,
author = {Hasan Irmak and
Nikolaos Alachiotis and
Daniel Ziener},
title = {An Energy-Efficient FPGA-based Convolutional Neural Network Implementation},
booktitle = {29th Signal Processing and Communications Applications Conference,
{SIU} 2021, Istanbul, Turkey, June 9-11, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/SIU53274.2021.9477823},
doi = {10.1109/SIU53274.2021.9477823},
timestamp = {Mon, 09 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/siu/IrmakAZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/VosKZ20,
author = {Pepijn de Vos and
Michael Kirchhoff and
Daniel Ziener},
title = {A Complete Open Source Design Flow for Gowin FPGAs},
booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT}
2020, Maui, HI, USA, December 9-11, 2020},
pages = {182--189},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICFPT51103.2020.00033},
doi = {10.1109/ICFPT51103.2020.00033},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/VosKZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icfpt/AsgharLKZ19,
author = {Ali Asghar and
Rick van Loo and
Timon Kruiper and
Daniel Ziener},
title = {Optimizing FPGA-Based Streaming Applications for Throughput Using
Pipelining},
booktitle = {International Conference on Field-Programmable Technology, {FPT} 2019,
Tianjin, China, December 9-13, 2019},
pages = {351--354},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICFPT47387.2019.00065},
doi = {10.1109/ICFPT47387.2019.00065},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icfpt/AsgharLKZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/PosewskyZ18,
author = {Thorbj{\"{o}}rn Posewsky and
Daniel Ziener},
title = {Throughput optimizations for FPGA-based deep neural network inference},
journal = {Microprocess. Microsystems},
volume = {60},
pages = {151--161},
year = {2018},
url = {https://doi.org/10.1016/j.micpro.2018.04.004},
doi = {10.1016/J.MICPRO.2018.04.004},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mam/PosewskyZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/PosewskyZ18,
author = {Thorbj{\"{o}}rn Posewsky and
Daniel Ziener},
editor = {Mladen Berekovic and
Rainer Buchty and
Heiko Hamann and
Dirk Koch and
Thilo Pionteck},
title = {A Flexible FPGA-Based Inference Architecture for Pruned Deep Neural
Networks},
booktitle = {Architecture of Computing Systems - {ARCS} 2018 - 31st International
Conference, Braunschweig, Germany, April 9-12, 2018, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10793},
pages = {311--323},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-3-319-77610-1\_23},
doi = {10.1007/978-3-319-77610-1\_23},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arcs/PosewskyZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/ZienerPT18,
author = {Daniel Ziener and
Jutta Pirkl and
J{\"{u}}rgen Teich},
editor = {David Andrews and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Dirk Stroobandt},
title = {Configuration Tampering of BRAM-based {AES} Implementations on FPGAs},
booktitle = {2018 International Conference on ReConFigurable Computing and FPGAs,
ReConFig 2018, Cancun, Mexico, December 3-5, 2018},
pages = {1--7},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/RECONFIG.2018.8641692},
doi = {10.1109/RECONFIG.2018.8641692},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/ZienerPT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1809-11156,
author = {Daniel Ziener},
title = {Improving Reliability, Security, and Efficiency of Reconfigurable
Hardware Systems},
journal = {CoRR},
volume = {abs/1809.11156},
year = {2018},
url = {http://arxiv.org/abs/1809.11156},
eprinttype = {arXiv},
eprint = {1809.11156},
timestamp = {Fri, 05 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1809-11156.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1810-00722,
author = {Thorbj{\"{o}}rn Posewsky and
Daniel Ziener},
title = {Throughput Optimizations for FPGA-based Deep Neural Network Inference},
journal = {CoRR},
volume = {abs/1810.00722},
year = {2018},
url = {http://arxiv.org/abs/1810.00722},
eprinttype = {arXiv},
eprint = {1810.00722},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1810-00722.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/basesearch/Ziener17,
author = {Daniel Ziener},
title = {Improving Reliability, Security, and Efficiency of Reconfigurable
Hardware Systems},
school = {University of Erlangen-Nuremberg, Germany},
year = {2017},
url = {https://opus4.kobv.de/opus4-fau/frontdoor/index/index/docId/9271},
urn = {urn:nbn:de:bvb:29-opus4-92715},
timestamp = {Tue, 16 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/basesearch/Ziener17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SchmidtZTZ17,
author = {Bernhard Schmidt and
Daniel Ziener and
J{\"{u}}rgen Teich and
Christian Z{\"{o}}llner},
title = {Optimizing scrubbing by netlist analysis for {FPGA} configuration
bit classification and floorplanning},
journal = {Integr.},
volume = {59},
pages = {98--108},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.06.012},
doi = {10.1016/J.VLSI.2017.06.012},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/SchmidtZTZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/SchmidtZTZ17,
author = {Bernhard Schmidt and
Daniel Ziener and
J{\"{u}}rgen Teich and
Christian Z{\"{o}}llner},
title = {Optimizing Scrubbing by Netlist Analysis for {FPGA} Configuration
Bit Classification and Floorplanning},
journal = {CoRR},
volume = {abs/1707.08134},
year = {2017},
url = {http://arxiv.org/abs/1707.08134},
eprinttype = {arXiv},
eprint = {1707.08134},
timestamp = {Tue, 30 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/SchmidtZTZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZienerBBDMSTVW16,
author = {Daniel Ziener and
Florian Bauer and
Andreas Becher and
Christopher Dennl and
Klaus Meyer{-}Wegener and
Ute Sch{\"{u}}rfeld and
J{\"{u}}rgen Teich and
J{\"{o}}rg{-}Stephan Vogt and
Helmut Weber},
title = {FPGA-Based Dynamically Reconfigurable {SQL} Query Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {25:1--25:24},
year = {2016},
url = {https://doi.org/10.1145/2845087},
doi = {10.1145/2845087},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZienerBBDMSTVW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/BecherEZWT16,
author = {Andreas Becher and
Jorge Echavarria and
Daniel Ziener and
Stefan Wildermann and
J{\"{u}}rgen Teich},
title = {A LUT-Based Approximate Adder},
booktitle = {24th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2016, Washington, DC, USA, May 1-3, 2016},
pages = {27},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/FCCM.2016.16},
doi = {10.1109/FCCM.2016.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/BecherEZWT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/EchavarriaWBTZ16,
author = {Jorge Echavarria and
Stefan Wildermann and
Andreas Becher and
J{\"{u}}rgen Teich and
Daniel Ziener},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {{FAU:} Fast and error-optimized approximate adder units on LUT-Based
FPGAs},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {213--216},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929536},
doi = {10.1109/FPT.2016.7929536},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/EchavarriaWBTZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/PosewskyZ16,
author = {Thorbj{\"{o}}rn Posewsky and
Daniel Ziener},
editor = {Peter M. Athanas and
Ren{\'{e}} Cumplido and
Claudia Feregrino and
Ron Sass},
title = {Efficient deep neural network acceleration through FPGA-based batch
processing},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
pages = {1--8},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ReConFig.2016.7857167},
doi = {10.1109/RECONFIG.2016.7857167},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/PosewskyZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/daglib/p/KochZH16,
author = {Dirk Koch and
Daniel Ziener and
Frank Hannig},
editor = {Dirk Koch and
Frank Hannig and
Daniel Ziener},
title = {{FPGA} Versus Software Programming: Why, When, and How?},
booktitle = {FPGAs for Software Programmers},
pages = {1--21},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-26408-0\_1},
doi = {10.1007/978-3-319-26408-0\_1},
timestamp = {Thu, 14 Oct 2021 08:45:49 +0200},
biburl = {https://dblp.org/rec/books/daglib/p/KochZH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/daglib/0040430,
editor = {Dirk Koch and
Frank Hannig and
Daniel Ziener},
title = {FPGAs for Software Programmers},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-26408-0},
doi = {10.1007/978-3-319-26408-0},
isbn = {978-3-319-26406-6},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/daglib/0040430.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/GleinRBZFTH15,
author = {Rob{\'{e}}rt Glein and
Florian Rittner and
Andreas Becher and
Daniel Ziener and
J{\"{u}}rgen Frickel and
J{\"{u}}rgen Teich and
Albert Heuberger},
title = {Reliability of space-grade vs. {COTS} SRAM-based {FPGA} in N-modular
redundancy},
booktitle = {2015 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2015, Montreal, QC, Canada, June 15-18, 2015},
pages = {1--8},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/AHS.2015.7231159},
doi = {10.1109/AHS.2015.7231159},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ahs/GleinRBZFTH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/BecherZMT15,
author = {Andreas Becher and
Daniel Ziener and
Klaus Meyer{-}Wegener and
J{\"{u}}rgen Teich},
title = {A co-design approach for accelerated {SQL} query processing via FPGA-based
data filtering},
booktitle = {2015 International Conference on Field Programmable Technology, {FPT}
2015, Queenstown, New Zealand, December 7-9, 2015},
pages = {192--195},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPT.2015.7393148},
doi = {10.1109/FPT.2015.7393148},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpt/BecherZMT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/HannigKZ15,
author = {Frank Hannig and
Dirk Koch and
Daniel Ziener},
title = {Proceedings of the Second International Workshop on FPGAs for Software
Programmers {(FSP} 2015)},
journal = {CoRR},
volume = {abs/1508.06320},
year = {2015},
url = {http://arxiv.org/abs/1508.06320},
eprinttype = {arXiv},
eprint = {1508.06320},
timestamp = {Sat, 23 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/HannigKZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/GleinSRTZ14,
author = {Rob{\'{e}}rt Glein and
Bernhard Schmidt and
Florian Rittner and
J{\"{u}}rgen Teich and
Daniel Ziener},
title = {A Self-Adaptive {SEU} Mitigation System for FPGAs with an Internal
Block {RAM} Radiation Particle Sensor},
booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014},
pages = {251--258},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FCCM.2014.79},
doi = {10.1109/FCCM.2014.79},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/GleinSRTZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SchmidtZT14,
author = {Bernhard Schmidt and
Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Vaughn Betz and
George A. Constantinides},
title = {An automatic netlist and floorplanning approach to improve the {MTTR}
of scrubbing techniques (abstract only)},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {257},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554730},
doi = {10.1145/2554688.2554730},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SchmidtZT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/BecherBZT14,
author = {Andreas Becher and
Florian Bauer and
Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Energy-aware {SQL} query acceleration through FPGA-based dynamic partial
reconfiguration},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927502},
doi = {10.1109/FPL.2014.6927502},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/BecherBZT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/SchmidtZT14,
author = {Bernhard Schmidt and
Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Minimizing Scrubbing Effort through Automatic Netlist Partitioning
and Floorplanning},
booktitle = {2014 {IEEE} International Parallel {\&} Distributed Processing
Symposium Workshops, Phoenix, AZ, USA, May 19-23, 2014},
pages = {299--304},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/IPDPSW.2014.41},
doi = {10.1109/IPDPSW.2014.41},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/SchmidtZT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/HannigKZ14,
author = {Frank Hannig and
Dirk Koch and
Daniel Ziener},
title = {Proceedings of the First International Workshop on FPGAs for Software
Programmers {(FSP} 2014)},
journal = {CoRR},
volume = {abs/1408.4423},
year = {2014},
url = {http://arxiv.org/abs/1408.4423},
eprinttype = {arXiv},
eprint = {1408.4423},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/HannigKZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/WildermannRZT13,
author = {Stefan Wildermann and
Felix Reimann and
Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Symbolic system-level design methodology for multi-mode reconfigurable
systems},
journal = {Des. Autom. Embed. Syst.},
volume = {17},
number = {2},
pages = {343--375},
year = {2013},
url = {https://doi.org/10.1007/s10617-012-9102-1},
doi = {10.1007/S10617-012-9102-1},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/WildermannRZT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/DennlZT13,
author = {Christopher Dennl and
Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Acceleration of {SQL} Restrictions and Aggregations through FPGA-Based
Dynamic Partial Reconfiguration},
booktitle = {21st {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2013, Seattle, WA, USA, April 28-30, 2013},
pages = {25--28},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/FCCM.2013.38},
doi = {10.1109/FCCM.2013.38},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/DennlZT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arcs/KochTBZDBTFS11,
author = {Dirk Koch and
Jim T{\o}rresen and
Christian Beckhoff and
Daniel Ziener and
Christopher Dennl and
Volker Breuer and
J{\"{u}}rgen Teich and
Michael Feilen and
Walter Stechele},
editor = {Gero M{\"{u}}hl and
Jan Richling and
Andreas Herkersdorf},
title = {Partial Reconfiguration on FPGAs in Practice - Tools and Applications},
booktitle = {{ARCS} 2012 Workshops, 28. Februar - 2. M{\"{a}}rz 2012, M{\"{u}}nchen,
Germany},
series = {{LNI}},
volume = {{P-200}},
pages = {297--319},
publisher = {{GI}},
year = {2012},
url = {https://ieeexplore.ieee.org/document/6222217/},
timestamp = {Tue, 04 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arcs/KochTBZDBTFS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/DennlZT12,
author = {Christopher Dennl and
Daniel Ziener and
J{\"{u}}rgen Teich},
title = {On-the-fly Composition of FPGA-Based {SQL} Query Accelerators Using
a Partially Reconfigurable Module Library},
booktitle = {2012 {IEEE} 20th Annual International Symposium on Field-Programmable
Custom Computing Machines, {FCCM} 2012, 29 April - 1 May 2012, Toronto,
Ontario, Canada},
pages = {45--52},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/FCCM.2012.18},
doi = {10.1109/FCCM.2012.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/DennlZT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/ZiermannBTZ12,
author = {Tobias Ziermann and
Alexander Butiu and
J{\"{u}}rgen Teich and
Daniel Ziener},
title = {FPGA-based testbed for timing behavior evaluation of the Controller
Area Network {(CAN)}},
booktitle = {2012 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2012, Cancun, Mexico, December 5-7, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ReConFig.2012.6416750},
doi = {10.1109/RECONFIG.2012.6416750},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/ZiermannBTZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/WildermannRZT11,
author = {Stefan Wildermann and
Felix Reimann and
Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Robert P. Dick and
Jan Madsen},
title = {Symbolic design space exploration for multi-mode reconfigurable systems},
booktitle = {Proceedings of the 9th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2011, part of ESWeek '11
Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011},
pages = {129--138},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2039370.2039393},
doi = {10.1145/2039370.2039393},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/WildermannRZT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AngermeierZGT11,
author = {Josef Angermeier and
Daniel Ziener and
Michael Gla{\ss} and
J{\"{u}}rgen Teich},
title = {Stress-Aware Module Placement on Reconfigurable Devices},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {277--281},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.56},
doi = {10.1109/FPL.2011.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/AngermeierZGT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/WildermannTZ11,
author = {Stefan Wildermann and
J{\"{u}}rgen Teich and
Daniel Ziener},
title = {Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous
Reconfigurable SoCs},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {429--434},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.85},
doi = {10.1109/FPL.2011.85},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/WildermannTZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/AngermeierZGT11,
author = {Josef Angermeier and
Daniel Ziener and
Michael Gla{\ss} and
J{\"{u}}rgen Teich},
editor = {Russell Tessier},
title = {Runtime stress-aware replica placement on reconfigurable devices under
safety constraints},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6133247},
doi = {10.1109/FPT.2011.6133247},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/AngermeierZGT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZiermannSMZAT11,
author = {Tobias Ziermann and
Bernhard Schmidt and
Moritz M{\"{u}}hlenthaler and
Daniel Ziener and
Josef Angermeier and
J{\"{u}}rgen Teich},
editor = {Russell Tessier},
title = {An {FPGA} implementation of a threat-based strategy for Connect6},
booktitle = {2011 International Conference on Field-Programmable Technology, {FPT}
2011, New Delhi, India, December 12-14, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/FPT.2011.6133250},
doi = {10.1109/FPT.2011.6133250},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ZiermannSMZAT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@phdthesis{DBLP:phd/de/Ziener2010,
author = {Daniel Ziener},
title = {Techniques for Increasing Security and Reliability of {IP} Cores Embedded
in {FPGA} and {ASIC} Designs},
school = {University of Erlangen-Nuremberg},
year = {2010},
url = {http://www.dr.hut-verlag.de/978-3-86853-657-7.html},
urn = {urn:nbn:de:101:1-201012149937},
isbn = {978-3-86853-657-7},
timestamp = {Sat, 17 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/phd/de/Ziener2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MayWBZSHZT10,
author = {Matthias May and
Norbert Wehn and
Abdelmajid Bouajila and
Johannes Zeppenfeld and
Walter Stechele and
Andreas Herkersdorf and
Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {A rapid prototyping system for error-resilient multi-processor systems-on-chip},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {375--380},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457176},
doi = {10.1109/DATE.2010.5457176},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MayWBZSHZT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ZienerBT10,
author = {Daniel Ziener and
Florian Baueregger and
J{\"{u}}rgen Teich},
editor = {Ron Sass and
Russell Tessier},
title = {Using the Power Side Channel of FPGAs for Communication},
booktitle = {18th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2010, Charlotte, North Carolina, USA, 2-4
May 2010},
pages = {237--244},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FCCM.2010.43},
doi = {10.1109/FCCM.2010.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ZienerBT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/ZienerBT10,
author = {Daniel Ziener and
Florian Baueregger and
J{\"{u}}rgen Teich},
editor = {Jim Plusquellic and
Ken Mai},
title = {Multiplexing Methods for Power Watermarking},
booktitle = {{HOST} 2010, Proceedings of the 2010 {IEEE} International Symposium
on Hardware-Oriented Security and Trust (HOST), 13-14 June 2010, Anaheim
Convention Center, California, {USA}},
pages = {36--41},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HST.2010.5513118},
doi = {10.1109/HST.2010.5513118},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/host/ZienerBT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dagstuhl/ZienerT10,
author = {Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Peter M. Athanas and
J{\"{u}}rgen Becker and
J{\"{u}}rgen Teich and
Ingrid Verbauwhede},
title = {New Directions for {IP} Core Watermarking and Identification},
booktitle = {Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010},
series = {Dagstuhl Seminar Proceedings},
volume = {10281},
publisher = {Schloss Dagstuhl - Leibniz-Zentrum f{\"{u}}r Informatik, Germany},
year = {2010},
url = {http://drops.dagstuhl.de/opus/volltexte/2010/2843/},
timestamp = {Thu, 10 Jun 2021 13:02:07 +0200},
biburl = {https://dblp.org/rec/conf/dagstuhl/ZienerT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijaacs/ZienerT09,
author = {Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Concepts for run-time and error-resilient control flow checking of
embedded {RISC} CPUs},
journal = {Int. J. Auton. Adapt. Commun. Syst.},
volume = {2},
number = {3},
pages = {256--275},
year = {2009},
url = {https://doi.org/10.1504/IJAACS.2009.026785},
doi = {10.1504/IJAACS.2009.026785},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijaacs/ZienerT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/ZienerT08,
author = {Daniel Ziener and
J{\"{u}}rgen Teich},
title = {Power Signature Watermarking of {IP} Cores for FPGAs},
journal = {J. Signal Process. Syst.},
volume = {51},
number = {1},
pages = {123--136},
year = {2008},
url = {https://doi.org/10.1007/s11265-007-0136-8},
doi = {10.1007/S11265-007-0136-8},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsisp/ZienerT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/atc/ZienerT08,
author = {Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Chunming Rong and
Martin Gilje Jaatun and
Frode Eika Sandnes and
Laurence Tianruo Yang and
Jianhua Ma},
title = {Concepts for Autonomous Control Flow Checking for Embedded CPUs},
booktitle = {Autonomic and Trusted Computing, 5th International Conference, {ATC}
2008, Oslo, Norway, June 23-25, 2008, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5060},
pages = {234--248},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-69295-9\_20},
doi = {10.1007/978-3-540-69295-9\_20},
timestamp = {Thu, 01 Feb 2024 20:40:31 +0100},
biburl = {https://dblp.org/rec/conf/atc/ZienerT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SchmidZT08,
author = {Moritz Schmid and
Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Netlist-level {IP} protection by watermarking for LUT-based FPGAs},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {209--216},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762385},
doi = {10.1109/FPT.2008.4762385},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SchmidZT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZienerAT06,
author = {Daniel Ziener and
Stefan Assmus and
J{\"{u}}rgen Teich},
title = {Identifying {FPGA} IP-Cores Based on Lookup Table Content Analysis},
booktitle = {Proceedings of the 2006 International Conference on Field Programmable
Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006},
pages = {1--6},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPL.2006.311255},
doi = {10.1109/FPL.2006.311255},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ZienerAT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZienerT06,
author = {Daniel Ziener and
J{\"{u}}rgen Teich},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {{FPGA} core watermarking based on power signature analysis},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
pages = {205--212},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270313},
doi = {10.1109/FPT.2006.270313},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ZienerT06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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