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ORCIDRobert H. Dennard
Person information
- affiliation: IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA
- award (2009): IEEE Medal of Honor
- award (2007): Benjamin Franklin Medal
- award (1988): National Medal of Technology and Innovation
- award: National Inventors Hall of Fame
- award: Kyoto Prize
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2010 – 2019
- 2010
[j14]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester
, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch:
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010)
2000 – 2009
- 2008
- [j13]Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek:
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches. IEEE J. Solid State Circuits 43(4): 956-963 (2008) - 2006
- [j12]Wilfried Haensch, Edward J. Nowak, Robert H. Dennard, Paul M. Solomon, Andres Bryant, Omer H. Dokumaci, Arvind Kumar, Xinlin Wang, Jeffrey B. Johnson, Massimo V. Fischetti:
Silicon CMOS devices beyond scaling. IBM J. Res. Dev. 50(4-5): 339-362 (2006) - 2005
- [j11]Wing K. Luk, Robert H. Dennard:
A novel dynamic memory cell with internal voltage gain. IEEE J. Solid State Circuits 40(4): 884-894 (2005) - [j10]Wing K. Luk, Robert H. Dennard:
Gated-diode amplifiers. IEEE Trans. Circuits Syst. II Express Briefs 52-II(5): 266-270 (2005) - 2002
- [j9]Jack A. Mandelman, Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, Rama Divakaruni, Yujun Li, Carl J. Raden:
Challenges and future directions for the scaling of dynamic random-access memory (DRAM). IBM J. Res. Dev. 46(2-3): 187-222 (2002) - 2001
- [j8]David J. Frank, Robert H. Dennard, Edward J. Nowak, Paul M. Solomon, Yuan Taur, Hon-Sum Philip Wong:
Device scaling limits of Si MOSFETs and their application dependencies. Proc. IEEE 89(3): 259-288 (2001) - 2000
- [j7]Dale L. Critchlow, Robert H. Dennard, Stanley Schuster:
Design and characteristics of n-channel insulated-gate field-effect transistors. IBM J. Res. Dev. 44(1): 70-83 (2000) - [j6]Osamu Takahashi, Sang H. Dhong, Manabu Ohkubo, Shohji Onishi, Robert H. Dennard, Robert Hannon, Scott Crowder, Subramanian S. Iyer, Matthew R. Wordeman, Bijan Davari, William B. Weinberger, Naoaki Aoki:
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. IEEE J. Solid State Circuits 35(11): 1673-1679 (2000)
1990 – 1999
- 1999
- [j5]Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous, Andre R. Leblanc:
Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions. Proc. IEEE 87(4): 668-678 (1999) - 1996
- [c2]Thomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly:
Iddq Testing for High Performance CMOS - The Next Ten Years. ED&TC 1996: 578-583 - [c1]Thomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly:
IDDQ Test: Sensitivity Analysis of Scaling. ITC 1996: 786-792 - 1995
- [j4]Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, J. Y.-C. Sun, Michael R. Polcari, Bijan Davari:
CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications. IBM J. Res. Dev. 39(1-2): 229-244 (1995) - [j3]Alina Deutsch, Gerard V. Kopcsay, Christopher W. Surovic, Barry J. Rubin, Lewis M. Terman, Richard P. Dunne Jr., Thomas A. Gallo, Robert H. Dennard:
Modeling and characterization of long on-chip interconnections for high-performance microprocessors. IBM J. Res. Dev. 39(5): 547-568 (1995) - [j2]Bijan Davari, Robert H. Dennard, Ghavam G. Shahidi:
CMOS scaling for high performance and low power-the next ten years. Proc. IEEE 83(4): 595-606 (1995)
1960 – 1969
- 1964
- [j1]Dale L. Critchlow, Robert H. Dennard, Emil Hopner:
A Vestigial-Sideband, Phase-Reversal Data Transmission System. IBM J. Res. Dev. 8(1): 33-42 (1964)
Coauthor Index
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