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Semantic ScholarPeeter Ellervee
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2010 – today
- 2017
[j7]Peeter Ellervee, Jari Nurmi:
Guest Editorial: Implementation Issues in System-on-Chip. Signal Processing Systems 87(3): 269-270 (2017)- 2016
- [j6]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen:
Polymorphic Configuration Architecture for CGRAs. IEEE Trans. VLSI Syst. 24(1): 403-407 (2016) - [c32]Priit Ruberg, Keijo Lass, Peeter Ellervee:
Data type dependent energy consumption estimation. NORCAS 2016: 1-5 - [c31]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee:
TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. PATMOS 2016: 92-99 - [c30]Siavoosh Payandeh Azad, Behrad Niazmand, Peeter Ellervee, Jaan Raik, Gert Jervan, Thomas Hollstein:
SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints. ReCoSoC 2016: 1-6 - 2015
- [j5]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
Functional self-test of high-performance pipe-lined signal processing architectures. Microprocessors and Microsystems - Embedded Hardware Design 39(8): 909-918 (2015) - [c29]Priit Ruberg, Aivar Guitar, Peeter Ellervee:
Flexible controller for educational robot kit. MSE 2015: 17-20 - [c28]Siavoosh Payandeh Azad, Hannes Kinks, Muhammad Adeel Tajammul, Peeter Ellervee:
An ad-hoc implementation of a remote laboratory. MSE 2015: 48-51 - [c27]Muhammad Adeel Tajammul, Siavoosh Payandeh Azad, Peeter Ellervee:
Digital system modeling and synthesis as an introduction to Computer Systems Engineering. MSE 2015: 52-55 - [c26]Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila:
DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. VLSI Design 2015: 547-552 - 2014
- [c25]Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD 2014: 42-49 - [c24]Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen:
Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM 2014: 31 - [e2]Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki:
2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014. IEEE 2014, ISBN 978-1-4799-6890-9 [contents] - 2013
- [j4]Peeter Ellervee, Jari Nurmi:
Guest Editorial. Microprocessors and Microsystems - Embedded Hardware Design 37(4-5): 430-431 (2013) - [c23]Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min:
At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP 2013: 1-6 - [e1]Jari Nurmi, Peeter Ellervee, Leandro Soares Indrusiak, Olli Vainio, Sarang Thombre, Jussi Raasakka:
2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013. IEEE 2013, ISBN 978-1-4799-1189-9 [contents] - 2012
- [c22]Maksim Gorev, Vadim Pesonen, Peeter Ellervee:
Multisine signal generation method for a bioimpedance measurement device. DDECS 2012: 111-114 - 2011
- [c21]Mihkel Tagel, Peeter Ellervee, Thorsten Hollstein, Gert Jervan:
Communication modelling and synthesis for NoC-based systems with real-time constraints. DDECS 2011: 237-242 - [c20]Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee:
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT 2011: 164-170 - [c19]Uljana Reinsalu, Peeter Ellervee:
Experience in increase of practical hours for HDL course. MSE 2011: 102-105 - [c18]Mihkel Tagel, Peeter Ellervee, Thomas Hollstein, Gert Jervan:
Contention aware scheduling for NoC-based real-time systems. NORCHIP 2011: 1-4 - 2010
- [j3]Peeter Ellervee, Gert Jervan:
Guest Editorial. Microprocessors and Microsystems - Embedded Hardware Design 34(5): 117 (2010)
2000 – 2009
- 2008
- [c17]Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee:
Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206 - [c16]Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee:
Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227 - 2007
- [j2]Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar:
FPGA-based fault emulation of synchronous sequential circuits. IET Computers & Digital Techniques 1(2): 70-76 (2007) - [c15]Uljana Reinsalu, Anton Arhipov, Teet Evartson, Peeter Ellervee:
HDL-s for Students with Different Background. MSE 2007: 69-70 - 2006
- [c14]Gert Jervan, Anton Arhipov, Peeter Ellervee:
Work in Progress: FPGA Based Emulation Environment. ReCoSoC 2006: 146-151 - 2005
- [c13]Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar:
Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78 - 2004
- [c12]Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe:
Evaluating Fault Emulation on FPGA. FPL 2004: 354-363 - 2002
- [c11]Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy:
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. ISSS 2002: 225-230 - 2001
- [j1]Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani:
System-level data-format exploration for dynamically allocated datastructures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1469-1472 (2001) - [c10]Peeter Ellervee, Hannu Tenhunen:
Digital Hardware Organization Course for SoC Program. MSE 2001: 26-27 - 2000
- [c9]Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani:
System-level data format exploration for dynamically allocated data structures. DAC 2000: 556-559 - [c8]Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs. DATE 2000: 751
1990 – 1999
- 1999
- [c7]Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist:
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. DAC 1999: 873-878 - [c6]Peeter Ellervee, Ahmed Hemani, Miguel Miranda, Francky Catthoor:
Exploiting Data Transfer Locality in Memory Mapping. EUROMICRO 1999: 1014-1021 - [c5]Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen:
Globally asynchronous locally synchronous architecture for large high-performance ASICs. ISCAS (2) 1999: 512-515 - 1998
- [c4]Johnny Öberg, Peeter Ellervee:
Revolver: A High-Performance MIMD Architecture for Collision Free Computing. EUROMICRO 1998: 10301- - 1996
- [c3]Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen:
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. VLSI Design 1996: 23-28 - [c2]Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani:
A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. VLSI Design 1996: 133-139 - 1994
- [c1]Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen:
Hardware/software partitioning and minimizing memory interface traffic. EURO-DAC 1994: 226-231
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last updated on 2017-09-17 23:47 CEST by the dblp team