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Siva Satyendra Sahoo
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2020 – today
- 2023
- [j8]Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories. IEEE Embed. Syst. Lett. 15(4): 170-173 (2023) - [j7]Siva Satyendra Sahoo, Salim Ullah, Akash Kumar:
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators. ACM Trans. Embed. Comput. Syst. 22(5s): 101:1-101:26 (2023) - [c18]Rohit Ranjan, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
SyFAxO-GeN: Synthesizing FPGA-Based Approximate Operators with Generative Networks. ASP-DAC 2023: 402-409 - [c17]Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
CoOAx: Correlation-aware Synthesis of FPGA-based Approximate Operators. ACM Great Lakes Symposium on VLSI 2023: 671-677 - [i3]Siva Satyendra Sahoo, Salim Ullah, Soumyo Bhattacharjee, Akash Kumar:
AxOCS: Scaling FPGA-based Approximate Operators using Configuration Supersampling. CoRR abs/2309.12830 (2023) - [i2]Siva Satyendra Sahoo, Salim Ullah, Akash Kumar:
AxOMaP: Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming. CoRR abs/2309.13445 (2023) - 2022
- [j6]Behnaz Ranjbar, Ali Hosseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar:
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3239-3251 (2022) - [j5]Salim Ullah, Siva Satyendra Sahoo, Nemath Ahmed, Debabrata Chaudhury, Akash Kumar:
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems. ACM Trans. Embed. Comput. Syst. 21(3): 29:1-29:31 (2022) - [c16]Amritha Immaneni, Salim Ullah, Suresh Nambi, Siva Satyendra Sahoo, Akash Kumar:
PosAx-O: Exploring Operator-level Approximations for Posit Arithmetic in Embedded AI/ML. DSD 2022: 214-223 - 2021
- [j4]Suresh Nambi, Salim Ullah, Siva Satyendra Sahoo, Aditya Lohana, Farhad Merchant, Akash Kumar:
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-Based Systems. IEEE Access 9: 103691-103708 (2021) - [j3]Salim Ullah, Hendrik Schmidl, Siva Satyendra Sahoo, Semeen Rehman, Akash Kumar:
Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures. IEEE Trans. Computers 70(3): 384-392 (2021) - [j2]Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(9): 1754-1767 (2021) - [c15]Siva Satyendra Sahoo, Akash Kumar, Martin Decky, Samuel Chang Bing Wong, Geoff V. Merrett, Yinyuan Zhao, Jiachen Wang, Xiaohang Wang, Amit Kumar Singh:
Emergent design challenges for embedded systems and paths forward: mixed-criticality, energy, reliability and security perspectives. CODES+ISSS 2021: 1-10 - [c14]Salim Ullah, Siva Satyendra Sahoo, Akash Kumar:
CLAppED: A Design Framework for Implementing Cross-Layer Approximation in FPGA-based Embedded Systems. DAC 2021: 475-480 - [c13]Behnaz Ranjbar, Ali Hoseinghorban, Siva Satyendra Sahoo, Alireza Ejlali, Akash Kumar:
Improving the Timing Behaviour of Mixed-Criticality Systems Using Chebyshev's Theorem. DATE 2021: 264-269 - [c12]Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, Akash Kumar:
MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems. ACM Great Lakes Symposium on VLSI 2021: 339-346 - [c11]Siva Satyendra Sahoo, Akash Kumar:
CLEO-CoDe: Exploiting Constrained Decoding for Cross-Layer Energy Optimization in Heterogeneous Embedded Systems. VLSI-SoC 2021: 1-6 - [c10]Siva Satyendra Sahoo, Akash Kumar:
Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems. VLSI-SoC 2021: 1-6 - 2020
- [c9]Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
CL(R)Early: An Early-stage DSE Methodology for Cross-Layer Reliability-aware Heterogeneous Embedded Systems. DAC 2020: 1-6 - [c8]Shubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar:
DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies. DATE 2020: 674-677 - [c7]Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems. DFT 2020: 1-6 - [i1]Suresh Nambi, Salim Ullah, Aditya Lohana, Siva Satyendra Sahoo, Farhad Merchant, Akash Kumar:
ExPAN(N)D: Exploring Posits for Efficient Artificial Neural Network Design in FPGA-based Systems. CoRR abs/2010.12869 (2020)
2010 – 2019
- 2019
- [j1]Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems. Integr. 67: 95-107 (2019) - [c6]Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded Systems. DAC 2019: 38 - 2018
- [c5]Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
Lifetime-aware design methodology for dynamic partially reconfigurable systems. ASP-DAC 2018: 393-398 - [c4]Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli, Akash Kumar:
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning. FPT 2018: 230-233 - [c3]Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
CLRFrame: An Analysis Framework for Designing Cross-Layer Reliability in Embedded Systems. VLSID 2018: 307-312 - 2016
- [c2]Siva Satyendra Sahoo, Akash Kumar, Bharadwaj Veeravalli:
Design and evaluation of reliability-oriented task re-mapping in MPSoCs using time-series analysis of intermittent faults. DATE 2016: 798-803 - [c1]Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar:
Cross-layer fault-tolerant design of real-time systems. DFT 2016: 63-68
Coauthor Index
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last updated on 2023-12-11 20:23 CET by the dblp team
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