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Tung Thanh Hoang
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Publications
- 2012
- [c6]Muhammad Waqar Azhar, Magnus Själander, Hasan Ali, Akshay Vijayashekar, Tung Thanh Hoang, Kashan Khurshid Ansari, Per Larsson-Edefors:
Viterbi Accelerator for Embedded Processor Datapaths. ASAP 2012: 133-140 - [c5]Tung Thanh Hoang, Per Larsson-Edefors:
Data-Width-Driven Power Gating of Integer Arithmetic Circuits. ISVLSI 2012: 237-242 - 2010
- [j1]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3073-3081 (2010) - [c4]Tung Thanh Hoang, Ulf Jalmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors:
Design space exploration for an embedded processor with flexible datapath interconnect. ASAP 2010: 55-62 - [c3]Muhammad Waqar Azhar, Tung Thanh Hoang, Per Larsson-Edefors:
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. DSD 2010: 675-680 - 2009
- [c2]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. IPDPS 2009: 1-7 - [c1]Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. SoCC 2009: 119-122
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last updated on 2023-10-01 22:29 CEST by the dblp team
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