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Ray C. C. Cheung
- > Home > Persons > Ray C. C. Cheung
Publications
- 2024
- [j89]Gaoyu Mao, Yao Liu, Wangchen Dai, Guangyan Li, Zhewen Zhang, Alan H. F. Lam, Ray C. C. Cheung:
REALISE-IoT: RISC-V-Based Efficient and Lightweight Public-Key System for IoT Applications. IEEE Internet Things J. 11(2): 3044-3055 (2024) - [j87]Junhao Huang, Alexandre Adomnicai, Jipeng Zhang, Wangchen Dai, Yao Liu, Ray C. C. Cheung, Çetin Kaya Koç, Donglong Chen:
Revisiting Keccak and Dilithium Implementations on ARMv7-M. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(2): 1-24 (2024) - 2023
- [c78]Shuo Liu, Qiaoling Wang, Junyi Zhang, Wenfei Wu, Qinliang Lin, Yao Liu, Meng Xu, Marco Canini, Ray C. C. Cheung, Jianfei He:
In-Network Aggregation with Transport Transparency for Distributed Training. ASPLOS (3) 2023: 376-391 - 2021
- [j68]Yao Liu, Junyi Zhang, Shuo Liu, Qiaoling Wang, Wangchen Dai, Ray Chak-Chung Cheung:
Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication. IEEE Trans. Circuits Syst. I Regul. Pap. 68(10): 4194-4206 (2021) - 2020
- [j64]Jingwei Hu, Yao Liu, Ray C. C. Cheung, Shivam Bhasin, San Ling, Huaxiong Wang:
Compact Code-Based Signature for Reconfigurable Devices With Side Channel Resilience. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2305-2316 (2020) - [i5]Shuo Liu, Qiaoling Wang, Junyi Zhang, Qinliang Lin, Yao Liu, Meng Xu, Ray C. C. Cheung, Jianfei He:
NetReduce: RDMA-Compatible In-Network Reduction for Distributed DNN Training Acceleration. CoRR abs/2009.09736 (2020) - 2019
- [c56]Zhenya Zang, Yao Liu, Ray C. C. Cheung:
Reconfigurable RISC-V Secure Processor And SoC Integration. ICIT 2019: 827-832 - 2018
- [j52]Yao Liu, Xiao-Zhou Li, Ray C. C. Cheung, Sze-Chun Chan, Hei Wong:
High-Speed Discrete Gaussian Sampler With Heterodyne Chaotic Laser Inputs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 794-798 (2018) - [c54]Yao Liu, Ray C. C. Cheung, Hei Wong:
Lightweight Secure Processor Prototype on FPGA. FPL 2018: 443-444 - 2017
- [j48]Yao Liu, Ray C. C. Cheung, Hei Wong:
A Bias-Bounded Digital True Random Number Generator Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 133-144 (2017)
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last updated on 2024-04-25 05:49 CEST by the dblp team
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