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Pranav Ashar
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Publications
- 2008
- [j18]Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1513-1517 (2008) - [j17]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based bounded model checking for software verification. Theor. Comput. Sci. 404(3): 256-274 (2008) - 2007
- [i1]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. CoRR abs/0710.4666 (2007) - 2006
- [j16]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient distributed SAT and SAT-based distributed Bounded Model Checking. Int. J. Softw. Tools Technol. Transf. 8(4-5): 387-396 (2006) - 2005
- [c46]Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar:
F-Soft: Software Verification Platform. CAV 2005: 301-306 - [c45]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Beyond safety: customized SAT-based model checking. DAC 2005: 738-743 - [c44]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Verification of Embedded Memory Systems using Efficient Memory Modeling. DATE 2005: 1096-1101 - [c43]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems. TACAS 2005: 575-580 - [c42]Aarti Gupta, Malay K. Ganai, Pranav Ashar:
Lazy Constraints and SAT Heuristics for Proof-Based Abstraction. VLSI Design 2005: 183-188 - 2004
- [c41]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient Modeling of Embedded Memories in Bounded Model Checking. CAV 2004: 440-452 - [c40]Malay K. Ganai, Aarti Gupta, Pranav Ashar:
Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. ICCAD 2004: 510-517 - [c39]Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang:
Efficient SAT-based Bounded Model Checking for Software Verification. ISoLA (Preliminary proceedings) 2004: 157-164 - 2003
- [c38]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Abstraction and BDDs Complement SAT-Based BMC in DiVer. CAV 2003: 206-209 - [c37]Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar:
Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking. CHARME 2003: 334-347 - [c36]Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar:
Learning from BDDs in SAT-based bounded model checking. DAC 2003: 824-829 - [c35]Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar:
Iterative Abstraction using SAT-based BMC with Proof Analysis. ICCAD 2003: 416-423 - 2002
- [c33]Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik:
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. DAC 2002: 747-750 - [c32]Aarti Gupta, Albert E. Casavant, Pranav Ashar, Sean Liu, Akira Mukaiyama, Kazutoshi Wakabayashi:
Property-Specific Testbench Generation for Guided Simulation. ASP-DAC/VLSI Design 2002: 524- - 2001
- [j14]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ACM Trans. Design Autom. Electr. Syst. 6(4): 569-590 (2001) - [c31]Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav Ashar:
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation. DAC 2001: 536-541 - [c30]Albert E. Casavant, Aarti Gupta, S. Liu, Akira Mukaiyama, Kazutoshi Wakabayashi, Pranav Ashar:
Property-specific witness graph generation for guided simulation. DATE 2001: 799 - [c29]Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik:
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. ICCAD 2001: 286-292 - 2000
- [c28]Aarti Gupta, Zijiang Yang, Pranav Ashar, Anubhav Gupta:
SAT-Based Image Computation with Application in Reachability Analysis. FMCAD 2000: 354-371 - [c27]Aarti Gupta, Pranav Ashar:
Fast Error Diagnosis for Combinational Verification. VLSI Design 2000: 442-448 - 1999
- [c25]Aarti Gupta, Pranav Ashar, Sharad Malik:
Exploiting Retiming in a Guided Simulation Based Validation Methodology. CHARME 1999: 350-353 - [c22]Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation. ICCD 1999: 458-466 - 1998
- [c17]Aarti Gupta, Pranav Ashar:
Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. VLSI Design 1998: 222-225 - 1997
- [c16]Aarti Gupta, Sharad Malik, Pranav Ashar:
Toward Formalizing a Validation Methodology Using Simulation Coverage. DAC 1997: 740-745 - 1996
- [c14]Pranav Ashar, Aarti Gupta, Sharad Malik:
Using complete-1-distinguishability for FSM equivalence checking. ICCAD 1996: 346-353
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