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Shigeyoshi Watanabe

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Yasuyuki Miura

> Home > Persons > Shigeyoshi Watanabe

Publications

2017
[j13]
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  - journals/ieicet/FukaseMWR17
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  persistent URL:
  - https://dblp.org/rec/journals/ieicet/FukaseMWR17
Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman:
The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer. IEICE Trans. Inf. Syst. 100-D(10): 2478-2492 (2017)
2016
[c14]
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  dblp key:
  - conf/icce-tw/FukaseMWR16
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  - https://dblp.org/rec/conf/icce-tw/FukaseMWR16
Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman:
The performance evaluation of 3D torus using link-sharing method in NoC router. ICCE-TW 2016: 1-2
2015
[j12]
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  - electronic edition @ ijnc.org (open access)
  - no references & citations available
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  dblp key:
  - journals/ijnc/MiuraSFWM15
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  - https://dblp.org/rec/journals/ijnc/MiuraSFWM15
Yasuyuki Miura, Kentaro Shimozono, Naohisa Fukase, Shigeyoshi Watanabe, Kazuya Matoyama:
An Adaptive Routing Algorithm of 2-D Torus Network Based on Turn Model: The Communication Performance. Int. J. Netw. Comput. 5(1): 223-238 (2015)
2014
[j11]
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  - journals/ieicet/NinomiyaKMW14
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  - https://dblp.org/rec/journals/ieicet/NinomiyaKMW14
Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe:
Reconfigurable Circuit Design Based on Arithmetic Logic Unit Using Double-Gate CNTFETs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2): 675-678 (2014)
[j10]
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  dblp key:
  - journals/ieicet/KobayashiNMW14
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  - https://dblp.org/rec/journals/ieicet/KobayashiNMW14
Manabu Kobayashi, Hiroshi Ninomiya, Yasuyuki Miura, Shigeyoshi Watanabe:
Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(5): 1051-1058 (2014)
[c13]
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  - conf/ic-nc/FukaseMWR14
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Naohisa Fukase, Yasuyuki Miura, Shigeyoshi Watanabe, M. M. Hafizur Rahman:
The Proposal of Partial Sharing for Link-Sharing Method of Buffer in NoC Router. CANDAR 2014: 567-571
2013
[c12]
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  dblp key:
  - conf/ic-nc/MiuraMSW13
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  - https://dblp.org/rec/conf/ic-nc/MiuraMSW13
Yasuyuki Miura, Kazuya Matoyama, Kentaro Shimozono, Shigeyoshi Watanabe:
An Adaptive Routing of the 2-D Torus Network Based on Turn Model. CANDAR 2013: 587-591
2010
[c11]
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  - conf/ipcv/MiuraSMW10
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Yasuyuki Miura, Masato Suzuki, Ryo Morikawa, Shigeyoshi Watanabe:
Subtractive Color Process for Lossless Compression of Non-photographed Images. IPCV 2010: 615-621
[c10]
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  dblp key:
  - conf/lcn/MiuraKW10
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  - https://dblp.org/rec/conf/lcn/MiuraKW10
Yasuyuki Miura, Masahiro Kaneko, Shigeyoshi Watanabe:
Adaptive routing algorithms and implementation for interconnection network TESH for parallel processing. LCN 2010: 308-311

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