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Cliff C. N. Sze
- > Home > Persons > Cliff C. N. Sze
Publications
- 2014
- [j15]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst. 19(2): 17:1-17:37 (2014) - [c42]Nancy Y. Zhou, Phillip J. Restle, Joseph N. Palumbo, Joseph N. Kozhaya, Haifeng Qian, Zhuo Li, Charles J. Alpert, Cliff C. N. Sze:
Pacman: driving nonuniform clock grid loads for low-skew robust clock network. SLIP 2014: 3:1-3:5 - 2013
- [c41]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. ASP-DAC 2013: 350-355 - [c40]Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan:
Routing congestion estimation with real design constraints. DAC 2013: 92:1-92:8 - [c39]Yaoguang Wei, Zhuo Li, Cliff C. N. Sze, Shiyan Hu, Charles J. Alpert, Sachin S. Sapatnekar:
CATALYST: planning layer directives for effective design closure. DATE 2013: 1873-1878 - [c37]Samuel I. Ward, Natarajan Viswanathan, Nancy Y. Zhou, Cliff C. N. Sze, Zhuo Li, Charles J. Alpert, David Z. Pan:
Clock power minimization using structured latch templates and decision tree induction. ICCAD 2013: 599-606 - 2012
- [c35]Zhuo Li, Charles J. Alpert, Gi-Joon Nam, Cliff C. N. Sze, Natarajan Viswanathan, Nancy Y. Zhou:
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC 2012: 465-470 - [c34]Yaoguang Wei, Cliff C. N. Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi N. Reddy, Andrew D. Huber, Gustavo E. Téllez, Douglas Keller, Sachin S. Sapatnekar:
GLARE: global and local wiring aware routability evaluation. DAC 2012: 768-773 - [c33]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
The DAC 2012 routability-driven placement contest and benchmark suite. DAC 2012: 774-782 - [c32]Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. ACM Great Lakes Symposium on VLSI 2012: 327-332 - [c31]Charles J. Alpert, Zhuo Li, Gi-Joon Nam, Chin Ngai Sze, Natarajan Viswanathan, Samuel I. Ward:
Placement: Hot or Not? ICCAD 2012: 283-290 - [c30]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Yaoguang Wei:
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. ICCAD 2012: 345-348 - 2011
- [j12]David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. IEEE Micro 31(4): 51-62 (2011) - [j11]Nancy Ying Zhou, Charles J. Alpert, Zhuo Li, Cliff N. Sze, Louise Trevillyan:
Shedding Physical Synthesis Area Bloat. VLSI Design 2011: 503025:1-503025:10 (2011) - [c25]Samuel I. Ward, David A. Papa, Zhuo Li, Cliff N. Sze, Charles J. Alpert, Earl E. Swartzlander Jr.:
Quantifying academic placer performance on custom designs. ISPD 2011: 91-98 - [c24]Natarajan Viswanathan, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Gi-Joon Nam, Jarrod A. Roy:
The ISPD-2011 routability-driven placement contest and benchmark suite. ISPD 2011: 141-146 - 2010
- [c22]Zhuo Li, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou:
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ISPD 2010: 75-82 - 2009
- [c20]Cliff N. Sze, Phillip J. Restle, Gi-Joon Nam, Charles J. Alpert:
Ispd2009 clock network synthesis contest. ISPD 2009: 149-150 - 2008
- [j10]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2156-2168 (2008) - [c19]Tao Luo, David A. Papa, Zhuo Li, Chin Ngai Sze, Charles J. Alpert, David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211 - [c18]David A. Papa, Tao Luo, Michael D. Moffitt, Chin Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. ISPD 2008: 2-9 - 2007
- [j9]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
Techniques for Fast Physical Synthesis. Proc. IEEE 95(3): 573-599 (2007) - [j8]Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path-Based Buffer Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1346-1355 (2007) - [j7]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Chin Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2009-2022 (2007) - [c16]Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz:
The nuts and bolts of physical synthesis. SLIP 2007: 89-94 - 2006
- [j6]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1140-1145 (2006) - [c15]Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313 - [c14]Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang:
Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392 - 2005
- [c12]Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18 - [c8]Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. DAC 2005: 509-514 - 2004
- [j4]Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 517-526 (2004) - [c7]Cliff C. N. Sze, Jiang Hu, Charles J. Alpert:
A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360 - [c6]Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711
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