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Allen C.-H. Wu
- > Home > Persons > Allen C.-H. Wu
Publications
- 2021
- [j22]Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang:
A novel privacy-preserving deep learning scheme without a cryptography component. Comput. Electr. Eng. 94: 107325 (2021) - [c43]Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). ASP-DAC 2021: 210-215 - 2019
- [c42]Pei-An Ho, Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang:
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs. SoCC 2019: 236-241 - [c41]Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen C.-H. Wu, TingTing Hwang:
Crosstalk-aware TSV-buffer Insertion in 3D IC. SoCC 2019: 400-405 - [i1]Chin-Yu Sun, Allen C.-H. Wu, TingTing Hwang:
A Novel Privacy-Preserving Deep Learning Scheme without Using Cryptography Component. CoRR abs/1908.07701 (2019) - 2017
- [j21]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 820-832 (2017) - 2016
- [c40]Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang:
A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. DATE 2016: 79-84 - 2007
- [j20]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 564-573 (2007) - 2006
- [j19]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of instruction decoders for low-power designs. ACM Trans. Design Autom. Electr. Syst. 11(4): 880-889 (2006) - [j18]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 81-85 (2006) - [c38]Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-driven crosstalk elimination at post-compiler level. ISCAS 2006 - 2005
- [c37]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
A power-driven multiplication instruction-set design method for ASIPs. ISCAS (4) 2005: 3311-3314 - 2004
- [c35]Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
Decomposition of Instruction Decoder for Low Power Design. DATE 2004: 664-665 - 2003
- [c34]Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. DATE 2003: 11102-11103 - [c33]Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang:
G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. DATE 2003: 11134-11135 - 1995
- [j4]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995) - 1994
- [c10]Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
State Assignment for Power and Area Minimization. ICCD 1994: 250-254 - 1993
- [c9]Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs. ICCAD 1993: 123-127
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