Manuel E. Acacio

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Antonio Flores

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Publications

2019
[j34]
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J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio:
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30(11): 2608-2623 (2019)
2017
[c62]
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J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS 2017: 20:1-20:10
2010
[j13]
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  - journals/jsa/FloresAA10
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Antonio Flores, Manuel E. Acacio, Juan L. Aragón:
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. J. Syst. Archit. 56(9): 429-441 (2010)
[j12]
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Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. IEEE Trans. Computers 59(1): 16-28 (2010)
[c37]
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Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. PDP 2010: 147-154
2008
[j7]
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Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. J. Supercomput. 45(3): 341-364 (2008)
[c24]
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Antonio Flores, Manuel E. Acacio, Juan L. Aragón:
Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303
2007
[c20]
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  - conf/aina/FloresAA07
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Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757
[c19]
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Antonio Flores, Juan L. Aragón, Manuel E. Acacio:
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146

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