Stanislaw J. Piestrak

◀ ▶ joint publications with Olivier Sentieys

> Home > Persons > Stanislaw J. Piestrak

Publications

2014
[j18]
- view
  authority control:
- export record
  dblp key:
  - journals/mam/JafriPSP14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/mam/JafriPSP14
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014)
2011
[c24]
- view
  authority control:
- export record
  dblp key:
  - conf/ddecs/AzeemPSP11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ddecs/AzeemPSP11
Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. DDECS 2011: 441-446
2010
[j14]
- view
  authority control:
- export record
  dblp key:
  - journals/icl/PiestrakPS10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/icl/PiestrakPS10
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14(8): 761-763 (2010)
[j13]
- view
  authority control:
- export record
  dblp key:
  - journals/tcas/PiestrakPS10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/PiestrakPS10
Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 777-781 (2010)
[c19]
- view
  authority control:
- export record
  dblp key:
  - conf/isqed/JafriPSP10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isqed/JafriPSP10
Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852
1998
[c9]
- view
  - electronic edition @ ieee.org
  - no references & citations available
- export record
  dblp key:
  - conf/eusipco/PiestrakPS98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/eusipco/PiestrakPS98
Stanislaw J. Piestrak, Fabrice Pedron, Olivier Sentieys:
VLSI implementation and complexity comparison of residue generators modulo 3. EUSIPCO 1998: 1-4

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.