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ORCIDT. M. Mak
Publications
- 2015
[j15]Martin Omaña, Daniele Rossi
, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Asifur Rahman, Simon Tam:
Low-Cost On-Chip Clock Jitter Measurement Scheme. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 435-443 (2015)- 2014
- [j14]Daniele Rossi, Martin Omaña, José Manuel Cazeaux, Cecilia Metra, T. M. Mak:
Clock Faults Induced Min and Max Delay Violations. J. Electron. Test. 30(1): 111-123 (2014) - 2012
- [j13]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
New Design for Testability Approach for Clock Fault Testing. IEEE Trans. Computers 61(4): 448-457 (2012) - 2011
- [j11]Martin Omaña, Cecilia Metra, T. M. Mak, Simon Tam:
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2322-2325 (2011) - 2010
- [c44]Martin Omaña, Daniele Giaffreda, Cecilia Metra, T. M. Mak, Simon Tam, Asifur Rahman:
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. DFT 2010: 265-272 - 2008
- [c41]Cecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam:
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. DFT 2008: 465-473 - 2007
- [j9]Cecilia Metra, Daniele Rossi, T. M. Mak:
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?. IEEE Trans. Computers 56(3): 415-428 (2007) - [c35]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel compensation scheme for local clocks of high performance microprocessors. ITC 2007: 1-9 - [c34]Cecilia Metra, Martin Omaña, T. M. Mak, Simon Tam:
Novel Approach to Clock Fault Testing for High Performance Microprocessors. VTS 2007: 441-446 - 2006
- [c33]Cecilia Metra, Daniele Rossi, Martin Omaña, José Manuel Cazeaux, T. M. Mak:
Can Clock Faults be Detected Through Functional Test? DDECS 2006: 168-173 - [c31]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation. IOLTS 2006: 17-22 - 2005
- [c24]Cecilia Metra, Martin Omaña, Daniele Rossi, José Manuel Cazeaux, T. M. Mak:
The Other Side of the Timing Equation: a Result of Clock Faults. DFT 2005: 169-177 - 2004
- [j1]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing. IEEE Trans. Computers 53(5): 531-546 (2004) - [c19]Cecilia Metra, T. M. Mak, Martin Omaña:
Fault secureness need for next generation high performance microprocessor design for testability structures. Conf. Computing Frontiers 2004: 444-450 - [c16]Cecilia Metra, T. M. Mak, Martin Omaña:
Are Our Design for Testability Features Fault Secure? DATE 2004: 714-715 - [c12]Cecilia Metra, T. M. Mak, Martin Omaña:
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing. ITC 2004: 1223-1231 - 2003
- [c8]Cecilia Metra, T. M. Mak, Daniele Rossi:
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors. DFT 2003: 63-70 - 2002
- [c4]Cecilia Metra, Stefano Di Francescantonio, T. M. Mak:
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing. ITC 2002: 100-109 - 2001
- [c3]Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak:
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects. DFT 2001: 357-365
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