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Shivam Bhasin
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Publications
- 2021
- [j35]Ville Yli-Mäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma:
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - 2020
- [j31]Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020) - 2019
- [c71]Alexandre Menu, Shivam Bhasin, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger:
Precise Spatio-Temporal Electromagnetic Fault Injections on Data Transfers. FDTC 2019: 1-8 - 2018
- [j16]Debapriya Basu Roy, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He, Debdeep Mukhopadhyay, Zakaria Najm, Xuan Thuy Ngo:
The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA. J. Hardw. Syst. Secur. 2(2): 162-178 (2018) - 2017
- [j8]Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin:
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66(2): 354-360 (2017) - 2016
- [j6]Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger:
Method taking into account process dispersion to detect hardware Trojan Horse by side-channel analysis. J. Cryptogr. Eng. 6(3): 239-247 (2016) - [c41]Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger:
PLL to the rescue: a novel EM fault countermeasure. DAC 2016: 90:1-90:6 - [i9]Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger:
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. 2016: 522 (2016) - [i8]Pierre Belgarric, Shivam Bhasin, Nicolas Bruneau, Jean-Luc Danger, Nicolas Debande, Sylvain Guilley, Annelie Heuser, Zakaria Najm, Olivier Rioul:
Time-Frequency Analysis for Second-Order Attacks. IACR Cryptol. ePrint Arch. 2016: 772 (2016) - 2015
- [j5]Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger:
Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. 9(1): 1-13 (2015) - [j4]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He:
Exploiting FPGA Block Memories for Protected Cryptographic Implementations. ACM Trans. Reconfigurable Technol. Syst. 8(3): 16:1-16:16 (2015) - [c34]Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger:
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC 2015: 749-754 - [c33]Xuan Thuy Ngo, Ingrid Exurville, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm, Jean-Baptiste Rigaud, Bruno Robisson:
Hardware trojan detection by delay and electromagnetic measurements. DATE 2015: 782-787 - [c32]Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu Roy, Jean-Luc Danger, Sylvain Guilley:
Integrated Sensor: A Backdoor for Hardware Trojan Insertions? DSD 2015: 415-422 - [c30]Xuan Thuy Ngo, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses. HOST 2015: 82-87 - [c29]Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay:
From theory to practice of private circuit: A cautionary note. ICCD 2015: 296-303 - [c28]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT 2015: 1-4 - [c24]Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay, Xuan Thuy Ngo, Zakaria Najm:
Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications. SPACE 2015: 248-268 - [i5]Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger, Debdeep Mukhopadhyay:
Reconfigurable LUT: Boon or Bane for Secure Applications. IACR Cryptol. ePrint Arch. 2015: 120 (2015) - 2014
- [j3]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger:
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [c22]Xuan Thuy Ngo, Sylvain Guilley, Shivam Bhasin, Jean-Luc Danger, Zakaria Najm:
Encoding the state of integrated circuits: a proactive and reactive protection against hardware Trojans horses. WESS 2014: 7:1-7:10 - [c21]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c20]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c19]Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger:
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST 2014: 32-37 - [c18]Shivam Bhasin, Tarik Graba, Jean-Luc Danger, Zakaria Najm:
A look into SIMON from a side-channel perspective. HOST 2014: 56-59 - [c17]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
Side-channel leakage and trace compression using normalized inter-class variance. HASP@ISCA 2014: 7:1-7:9 - [c16]Shivam Bhasin, Nicolas Bruneau, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
Analysis and Improvements of the DPA Contest v4 Implementation. SPACE 2014: 201-218 - [i4]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage:
Hardware Trojan Horses in Cryptographic IP Cores. IACR Cryptol. ePrint Arch. 2014: 750 (2014) - [i3]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
Side-Channel Leakage and Trace Compression using Normalized Inter-Class Variance. IACR Cryptol. ePrint Arch. 2014: 1020 (2014) - 2013
- [j2]Shivam Bhasin, Sylvain Guilley, Annelie Heuser, Jean-Luc Danger:
From cryptography to hardware: analyzing and protecting embedded Xilinx BRAM for cryptographic applications. J. Cryptogr. Eng. 3(4): 213-225 (2013) - [c15]Pierre Belgarric, Shivam Bhasin, Nicolas Bruneau, Jean-Luc Danger, Nicolas Debande, Sylvain Guilley, Annelie Heuser, Zakaria Najm, Olivier Rioul:
Time-Frequency Analysis for Second-Order Attacks. CARDIS 2013: 108-122 - [c14]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
A low-entropy first-degree secure provable masking scheme for resource-constrained devices. WESS 2013: 7:1-7:10 - [c13]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Xuan Thuy Ngo, Laurent Sauvage:
Hardware Trojan Horses in Cryptographic IP Cores. FDTC 2013: 15-29 - [c12]Shivam Bhasin, Wei He, Sylvain Guilley, Jean-Luc Danger:
Exploiting FPGA block memories for protected cryptographic implementations. ReCoSoC 2013: 1-8 - [i1]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
NICV: Normalized Inter-Class Variance for Detection of Side-Channel Leakage. IACR Cryptol. ePrint Arch. 2013: 717 (2013) - 2012
- [c11]Youssef Souissi, Shivam Bhasin, Sylvain Guilley, Maxime Nassar, Jean-Luc Danger:
Towards Different Flavors of Combined Side Channel Attacks. CT-RSA 2012: 245-259 - [c10]Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger:
From Cryptography to Hardware: Analyzing Embedded Xilinx BRAM for Cryptographic Applications. MICRO Workshops 2012: 1-8 - 2011
- [j1]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger:
Security evaluation of application-specific integrated circuits and field programmable gate arrays against setup time violation attacks. IET Inf. Secur. 5(4): 181-190 (2011) - [c9]Youssef Souissi, Jean-Luc Danger, Sylvain Guilley, Shivam Bhasin, Maxime Nassar:
Embedded systems security: An evaluation methodology against Side Channel Attacks. DASIP 2011: 230-237 - [c8]Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger:
Efficient Dual-Rail Implementations in FPGA Using Block RAMs. ReConFig 2011: 261-267 - 2010
- [c7]Shivam Bhasin, Sylvain Guilley, Florent Flament, Nidhal Selmane, Jean-Luc Danger:
Countering early evaluation: an approach towards robust dual-rail precharge logic. WESS 2010: 6 - [c6]Shivam Bhasin, Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger:
Unrolling Cryptographic Circuits: A Simple Countermeasure Against Side-Channel Attacks. CT-RSA 2010: 195-207 - [c5]Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley:
BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. DATE 2010: 849-854 - [c4]Zouha Cherif, Florent Flament, Jean-Luc Danger, Shivam Bhasin, Sylvain Guilley, Hervé Chabanne:
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA. ReConFig 2010: 310-315 - 2009
- [c3]Nidhal Selmane, Shivam Bhasin, Sylvain Guilley, Tarik Graba, Jean-Luc Danger:
WDDL is Protected against Setup Time Violation Attacks. FDTC 2009: 73-83 - [c2]Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Nidhal Selmane:
Security Evaluation of Different AES Implementations Against Practical Setup Time Violation Attacks in FPGAs. HOST 2009: 15-21 - [c1]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218
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