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Kundan Nepal
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Publications
- 2021
- [c25]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar:
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC 2021: 319-323 - 2019
- [j11]Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35(6): 887-900 (2019) - [c20]Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Test Architecture for Fine Grained Capture Power Reduction. ICECS 2019: 558-561 - 2016
- [c15]Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter:
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW 2016: 46-52 - 2015
- [j9]Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan:
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 849-861 (2015) - 2013
- [c14]Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar:
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS 2013: 243-248 - 2012
- [j8]Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar:
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18(1): 14:1-14:19 (2012) - 2011
- [c12]Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar:
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS 2011: 211 - [c10]Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Enhancing online error detection through area-efficient multi-site implications. VTS 2011: 241-246 - 2010
- [j6]Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 788-801 (2010) - [c9]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI 2010: 131-134 - 2009
- [c8]Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar:
Detecting errors using multi-cycle invariance information. DATE 2009: 791-796 - [c7]Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal:
Compacting test vector sets via strategic use of implications. ICCAD 2009: 83-88 - 2008
- [c6]Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar:
Using Implications for Online Error Detection. ITC 2008: 1-10 - 2007
- [j5]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23(2-3): 255-266 (2007) - [c5]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE 2007: 576-581 - 2006
- [j4]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26(5): 19-27 (2006) - [j3]Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein:
Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1815-1830 (2006) - [c4]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing MRF based error correcting circuits for memory elements. DATE 2006: 792-793 - [c3]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI 2006: 149-152 - 2005
- [j2]R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein:
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 502-515 (2005) - [c2]Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise. DAC 2005: 485-490 - 2004
- [c1]Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein:
RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412
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