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Seng-Pan U
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Publications
- 2019
- [j43]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Franco Maloberti, Seng-Pan U, Rui Paulo Martins:
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 489-501 (2019) - [j42]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 481-485 (2019) - 2018
- [j40]Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins:
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 53(3): 850-860 (2018) - [j38]Xiaofeng Yang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 1819-1829 (2018) - [j37]Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins:
Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 416-420 (2018) - [j35]Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2279-2289 (2018) - [c90]Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins:
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC 2018: 235-238 - 2017
- [j34]Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins:
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52(10): 2576-2588 (2017) - [j32]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins:
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 111-115 (2017) - [j30]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1684-1695 (2017) - [j29]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(8): 1966-1976 (2017) - [j27]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 354-363 (2017) - [j26]Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Ben Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 364-374 (2017) - [j25]Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins:
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1168-1172 (2017) - [c84]Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC 2017: 285-288 - [c83]Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC 2017: 239-242 - [c80]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins:
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC 2017: 282-283 - 2016
- [j24]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51(2): 365-377 (2016) - [j23]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits 51(5): 1223-1234 (2016) - [j20]Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins:
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1203-1207 (2016) - [j19]Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins:
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2603-2607 (2016) - [c72]Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins:
A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. A-SSCC 2016: 145-148 - [c71]Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC 2016: 169-172 - 2015
- [c69]Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC 2015: 1-4 - [c68]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC 2015: 1-3 - 2014
- [j17]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 372-383 (2014) - [c66]Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins:
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC 2014: 211-214 - 2013
- [j15]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48(9): 2154-2169 (2013) - [c63]Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS 2013: 2239-2242 - 2012
- [j14]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47(11): 2614-2626 (2012) - [j13]He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47(11): 2763-2772 (2012) - [c53]Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC 2012: 86-87 - [c52]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC 2012: 90-91 - 2011
- [c51]Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC 2011: 61-64 - [c50]Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC 2011: 73-76 - [c49]Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC 2011: 233-236 - [c48]U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC 2011: 363-366 - [c46]He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC 2011: 188-190 - 2010
- [j11]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45(6): 1111-1121 (2010) - [c43]Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti:
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC 2010: 218-221 - [c40]Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins:
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS 2010: 4061-4064
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