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Philip Brisk
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Publications
- 2017
- [j26]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. ACM Trans. Embed. Comput. Syst. 16(5s): 125:1-125:19 (2017) - [c79]Lana Josipovic, Philip Brisk, Paolo Ienne:
From C to elastic circuits. ACSSC 2017: 121-125 - [c78]Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. DAC 2017: 5:1-5:6 - [c74]Lana Josipovic, Philip Brisk, Paolo Ienne:
An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134 - 2016
- [c71]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. FPL 2016: 1 - [e2]Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 [contents] - 2015
- [j21]Ali Galip Bayrak, Francesco Regazzoni, David Novo, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
Automatic Application of Power Analysis Countermeasures. IEEE Trans. Computers 64(2): 329-341 (2015) - 2014
- [j17]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage. ACM Trans. Archit. Code Optim. 11(2): 15:1-15:26 (2014) - [j14]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 62-75 (2014) - 2013
- [j13]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(5): 681-694 (2013) - [c58]Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne:
An EDA-friendly protection scheme against side-channel attacks. DATE 2013: 410-415 - 2012
- [c53]Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. DATE 2012: 1543-1548 - [c52]Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk:
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264 - [c49]Aanjhan Ranganathan, Ali Galip Bayrak, Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Counting stream registers: An efficient and effective snoop filter architecture. ICSAMOS 2012: 120-127 - 2011
- [j10]Hadi Parandeh-Afshar, Arkosnato Neogy, Philip Brisk, Paolo Ienne:
Compressor tree synthesis on commercial high-performance FPGAs. ACM Trans. Reconfigurable Technol. Syst. 4(4): 39:1-39:19 (2011) - [c44]Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, François-Xavier Standaert, Paolo Ienne:
A first step towards automatic application of power analysis countermeasures. DAC 2011: 230-235 - [c43]Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne:
Reducing the pressure on routing resources of FPGAs with generic logic chains. FPGA 2011: 237-246 - 2010
- [j9]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 341-354 (2010) - [j8]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1096-1109 (2010) - [j7]Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 578-590 (2010) - [c42]Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors. ASP-DAC 2010: 707-712 - [c41]Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. FPL 2010: 19-24 - [c40]Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne:
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions. HiPEAC 2010: 126-140 - 2009
- [j6]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. Des. Autom. Embed. Syst. 13(1-2): 115-137 (2009) - [j4]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 13:1-13:36 (2009) - [j3]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. ACM Trans. Reconfigurable Technol. Syst. 2(3): 19:1-19:42 (2009) - [c39]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Challenges in Automatic Optimization of Arithmetic Circuits. IEEE Symposium on Computer Arithmetic 2009: 213-218 - [c38]Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator. ASP-DAC 2009: 203-209 - [c37]Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219 - [c36]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Way Stealing: cache-assisted automatic instruction set extensions. DAC 2009: 31-36 - [c34]Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. FCCM 2009: 267-270 - [c33]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj:
3D configuration caching for 2D FPGAs. FPGA 2009: 286 - [c32]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Exploiting fast carry-chains of FPGAs for designing compressor trees. FPL 2009: 242-249 - [c31]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Using 3D integration technology to realize multi-context FPGAs. FPL 2009: 507-510 - [c30]Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. FPT 2009: 70-77 - [c29]Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne:
MPSoC Design Using Application-Specific Architecturally Visible Communication. HiPEAC 2009: 183-197 - [c28]Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Memory organization and data layout for instruction set extensions with architecturally visible storage. ICCAD 2009: 689-696 - [c27]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Iterative layering: Optimizing arithmetic circuits by structuring the information flow. ICCAD 2009: 797-804 - [c26]Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne:
Arithmetic optimization for custom instruction set synthesis. SASP 2009: 54-57 - [c25]Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne:
Introducing control-flow inclusion to support pipelining in custom instruction set extensions. SASP 2009: 114-121 - [c24]Jani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne:
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications. SiPS 2009: 115-120 - 2008
- [j2]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10): 1761-1774 (2008) - [c23]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs. ASP-DAC 2008: 138-143 - [c22]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions. ASP-DAC 2008: 334-339 - [c21]Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c20]Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon:
Speculative DMA for architecturally visible storage in instruction set extensions. CODES+ISSS 2008: 243-248 - [c19]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. DATE 2008: 1250-1255 - [c18]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. DATE 2008: 1256-1261 - [c17]Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
A novel FPGA logic block for improved arithmetic performance. FPGA 2008: 171-180 - [c16]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - 2007
- [c13]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Rethinking custom ISE identification: a new processor-agnostic method. CASES 2007: 125-134 - [c12]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
An optimistic and conservative register assignment heuristic for chordal graphs. CASES 2007: 209-217 - [c11]Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits. DAC 2007: 334-337 - [c10]Ajay Kumar Verma, Philip Brisk, Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. DAC 2007: 404-409 - [c9]Philip Brisk, Ajay Kumar Verma, Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. ICCAD 2007: 172-179
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