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ORCIDNithin Kumar Yernad Balachandra
Nithin Y. B. Kumar – Nithin Kumar Y. B. – Kumar Y. B. Nithin – Y. B. Nithin Kumar
Person information
- affiliation: National Institute of Technology Goa, Department of Electronics and Communication Engineering, India
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Journal Articles
- 2024
[j19]K. G. Shreeharsha, Siddharth R. K., M. H. Vasantha, Kumar Y. B. Nithin:
An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 12: 50126-50136 (2024)- 2023
- [j18]K. G. Shreeharsha
, Siddharth R. K., M. H. Vasantha, Y. B. Nithin Kumar:
Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. IEEE Access 11: 123577-123588 (2023) - 2021
- [j17]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, M. H. Vasantha:
Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. IEEE Access 9: 108119-108130 (2021) - [j16]P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar:
$\pm \, 0.5$ V, 254 $\upmu $W Second-Order Tunable Biquad Low-Pass Filter with 7.3 fJ FOM Using a Novel Low-Voltage Fully Balanced Current-Mode Circuit. Circuits Syst. Signal Process. 40(5): 2114-2134 (2021) - [j15]Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Ch. Keshava Gopal, Devesh Dwivedi:
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications. Integr. 81: 268-279 (2021) - [j14]P. S. Veerendranath, Vivek Sharma, M. H. Vasantha, Y. B. Nithin Kumar:
A Novel Complex Filter Design With Dual Feedback for High Frequency Wireless Receiver Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1748-1752 (2021) - 2020
- [j13]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
An Approximate Low-Power Lifting Scheme Using Reversible Logic. IEEE Access 8: 183367-183377 (2020) - [j12]Siddharth Rajkumar Kala, Sushma Chandaka, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra, Edoardo Bonizzoni:
6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. IET Circuits Devices Syst. 14(3): 340-346 (2020) - [j11]Vivek Sharma, Nithin Kumar Y. B., Vasantha M. H.:
IET Circuits, Devices & Systems. IET Circuits Devices Syst. 14(6): 881-891 (2020) - [j10]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Design and implementation of image kernels using reversible logic gates. IET Image Process. 14(16): 4110-4121 (2020) - [j9]Bipul Boro, Karri Manikantta Reddy, Nithin Y. B. Kumar, M. H. Vasantha:
Approximate radix-8 Booth multiplier for low power and high speed applications. Microelectron. J. 101: 104816 (2020) - [j8]Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. SN Comput. Sci. 1(6): 310 (2020) - [j7]Siddharth R. K., Y. Jaya Satyanarayana, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. IEEE Trans. Circuits Syst. 67-II(12): 2918-2922 (2020) - [j6]Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi:
Design of Approximate Booth Squarer for Error-Tolerant Computing. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1230-1241 (2020) - 2018
- [j5]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
An energy-efficient fault-aware core mapping in mesh-based network on chip systems. J. Netw. Comput. Appl. 105: 79-87 (2018) - [j4]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
Hardware implementation of fault tolerance NoC core mapping. Telecommun. Syst. 68(4): 621-630 (2018) - [j3]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
Energy-Aware and Reliability-Aware Mapping for NoC-Based Architectures. Wirel. Pers. Commun. 100(2): 213-225 (2018) - 2017
- [j2]Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
System level fault-tolerance core mapping and FPGA-based verification of NoC. Microelectron. J. 70: 16-26 (2017) - [j1]Naresh Kumar Reddy Beechu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
High-performance and energy-efficient fault-tolerance core mapping in NoC. Sustain. Comput. Informatics Syst. 16: 1-10 (2017)
Conference and Workshop Papers
- 2023
- [c49]R. D. Balaji, Siddharth R. K., Sanmitra Bharat Naik, Y. B. Nithin Kumar, M. H. Vasantha, Edoardo Bonizzoni:
A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. ISCAS 2023: 1-5 - [c48]Darshan Halliyavar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B., Sithara Raveendran:
Approximate Three-Operand Binary Adder for Error-Resilient Applications. iSES 2023: 287-291 - [c47]Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi:
A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. VLSID 2023: 1-6 - 2022
- [c46]Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, M. H. Vasantha:
On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. ISCAS 2022: 3428-3432 - 2021
- [c45]Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni:
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. ISCAS 2021: 1-5 - [c44]K. G. Shreeharsha, Charudatta Korde, M. H. Vasantha, Y. B. Nithin Kumar:
Training of Generative Adversarial Networks using Particle Swarm Optimization Algorithm. iSES 2021: 127-130 - [c43]Shiv Chandra Kumar, Siddharth R. K., Nithin Kumar Y. B., M. H. Vasantha:
A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. ISVLSI 2021: 19-24 - [c42]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Kumar Y. B. Nithin, M. H. Vasantha, Ramnath Kini:
A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. VLSID 2021: 252-257 - 2020
- [c41]Nitish Kumar, Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. iSES 2020: 167-170 - [c40]Tejas J. Shahane, Siddharth R. K., Kumar Y. B. Nithin, Vasantha M. H.:
A 1.8 V, Mode-Configurable Hybrid Smart ADC. iSES 2020: 216-220 - [c39]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., M. H. Vasantha, Ramnath Kini:
A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. iSES 2020: 277-280 - [c38]Suraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.:
A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. ISVLSI 2020: 48-53 - [c37]Sithara Raveendran, Pranose J. Edavoor, Nithin Kumar Y. B., M. H. Vasantha:
Reversible Logic Implementation of Image Denoising for Grayscale Images. MWSCAS 2020: 138-141 - [c36]Sanmitra Bharat Naik, Siddharth R. K., Anirban Chatterjee, Nithin Kumar Y. B., Vasantha M. H., Ramnath Kini:
A Wideband 12 Phase Ring Oscillator for 5G Applications. MWSCAS 2020: 885-888 - 2019
- [c35]Pradeep R., Siddharth R. K., Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Process Corner Calibration for Standard Cell Based Flash ADC. iSES 2019: 195-200 - [c34]Rahul E., Siddharth R. K., Vivek Sharma, M. H. Vasantha, Nithin Kumar Yernad Balachandra:
Two-Step Flash ADC Using Standard Cell Based Flash ADCs. iSES 2019: 292-295 - [c33]Sunil R., Siddharth R. K., Nithin Y. B. Kumar, M. H. Vasantha:
An Asynchronous Analog to Digital Converter for Video Camera Applications. ISVLSI 2019: 175-180 - [c32]Prasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability. ISVLSI 2019: 627-631 - [c31]Jagadeesh Pujar, Sithara Raveendran, Trilochan Panigrahi, Vasantha M. H., Nithin Kumar Y. B.:
Design and Analysis of Energy Efficient Reversible Logic based Full Adder. MWSCAS 2019: 339-342 - [c30]P. S. Veerendranath, Vivek Sharma, Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
Current Conveyor based Novel Gyrator filter for Biomedical Sensor Applications. TENCON 2019: 658-661 - 2018
- [c29]Purnima Kalekar, Prasad Vernekar, M. H. Vasantha, Y. B. Nithin Kumar, Edoardo Bonizzoni:
A 0.5 V Low Power DTMOS OTA-C Filter for ECG Sensing Applications. IEEE SENSORS 2018: 1-4 - [c28]Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha, Edoardo Bonizzoni:
A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. ISCAS 2018: 1-5 - [c27]Sampada Barve, Sithara Raveendran, Charudatta Korde, Trilochan Panigrahi, Nithin Y. B. Kumar, M. H. Vasantha:
FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. iSES 2018: 6-10 - [c26]Chetan Kamble, Siddharth R. K., Shivnarayan Patidar, M. H. Vasantha, Nithin Y. B. Kumar:
Design of Area-Power-Delay Efficient Square Root Carry Select Adder. iSES 2018: 80-85 - [c25]Anirudha Pandey, Karri Manikantta Reddy, Praveen Yadav, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Analysis of Approximate Multipliers for Error-Tolerant Applications. iSES 2018: 94-97 - [c24]Siddharth R. K., Sunil R., Nithin Y. B. Kumar, M. H. Vasantha, Edoardo Bonizzoni:
An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. ISVLSI 2018: 164-169 - [c23]Donel Anto, Abhijeet D. Taralkar, Kumar Y. B. Nithin, M. H. Vasantha:
Performance Enhancement of Split Length Compensated Operational Amplifiers. ISVLSI 2018: 608-613 - [c22]Karri Manikantta Reddy, M. H. Vasantha, Kumar Y. B. Nithin, Devesh Dwivedi:
Design of Approximate Dividers for Error Tolerant Applications. MWSCAS 2018: 496-499 - [c21]Praveen Yadav, Anirudha Pandey, Karri Manikantta Reddy, K. J. Ravi Prasad, M. H. Vasantha, Nithin Y. B. Kumar:
Low Power Approximate Multipliers With Truncated Carry Propagation for LSBs. MWSCAS 2018: 500-503 - [c20]Dhavala Shashidhar, Vivek Sharma, G. R. Prashanth, Nithin Y. B. Kumar, M. H. Vasantha:
Characterization of a Novel Low Leakage Power-Efficient Asymmetric 7T SRAM Cell. TENCON 2018: 1768-1773 - [c19]Sithara Raveendran, Pranose J. Edavoor, Nithin Y. B. Kumar, M. H. Vasantha:
Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. TENCON 2018: 1813-1817 - [c18]P. S. Veerendranath, M. H. Vasantha, Kumar Y. B. Nithin, Edoardo Bonizzoni:
A Novel Low Power G m-C Continuous-Time Analog Filter with Wide Tuning Range. VLSID 2018: 214-219 - 2017
- [c17]Anoop D, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra:
High Performance Sense Amplifier Based Flip Flop for Driver Applications. iNIS 2017: 129-132 - [c16]Sumit Khalapure, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. ISVLSI 2017: 585-588 - [c15]Rakhi R., Abhijeet D. Taralkar, M. H. Vasantha, Kumar Y. B. Nithin:
A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection. ISVLSI 2017: 589-593 - [c14]S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. ISVLSI 2017: 600-603 - 2016
- [c13]Pranose J. Edavoor, Sithara Raveendran, Arjun T. V., Sumesh K. P., Kumar Y. B. Nithin, M. H. Vasantha:
FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. ICCCNT 2016: 35:1-35:6 - [c12]Saurabh B. Kaurati, Nithin Y. B. Kumar, Shivnarayan Patidar, M. H. Vasantha:
Design and Implementation of Tunable Bandpass Filter for Biomedical Applications. iNIS 2016: 43-46 - [c11]S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin:
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI 2016: 105-109 - [c10]B. Naresh Kumar Reddy, M. H. Vasantha, Kumar Y. B. Nithin:
A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core. ISVLSI 2016: 146-151 - [c9]S. M. Mayur, Siddharth R. K., Kumar Y. B. Nithin, M. H. Vasantha:
Design of Low Power 5-Bit Hybrid Flash ADC. ISVLSI 2016: 343-348 - [c8]A. Venkatareddy, Sithara Raveendran, Kumar Y. B. Nithin, M. H. Vasantha:
Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. VLSID 2016: 202-206 - 2015
- [c7]Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha:
Low power, high speed error tolerant multiplier using approximate adders. VDAT 2015: 1-6 - 2013
- [c6]Kumar Y. B. Nithin, Hervé Caracciolo, Edoardo Bonizzoni, A. Parra, Franco Maloberti:
A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator. ISCAS 2013: 1998-2001 - [c5]Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti:
Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators. VLSI Design 2013: 221-226 - 2012
- [c4]Kumar Y. B. Nithin, Edoardo Bonizzoni, Amit Patra, Franco Maloberti:
Interference rejection in delay line based quadrature band-pass ΣΔ modulators. ISCAS 2012: 3005-3008 - 2009
- [c3]Aldo Pena-Perez, Kumar Y. B. Nithin, Edoardo Bonizzoni, Franco Maloberti:
Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers. ISCAS 2009: 2485-2488 - [c2]Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti:
Complex Cascaded Bandpass SigmaDelta ADC Design. ISCAS 2009: 3118-3121 - 2008
- [c1]Kumar Y. B. Nithin, Selçuk Talay, Franco Maloberti:
On the design of band-pass quadrature ΣΔ modulators. APCCAS 2008: 1228-1231
Coauthor Index
Siddharth R. K.
aka: Siddharth Rajkumar Kala
aka: Siddharth Rajkumar Kala
[j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7]
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