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ORCIDRob A. Rutenbar
Person information
- affiliation: University of Pittsburgh, PA, USA
- affiliation (former): Carnegie Mellon University, Pittsburgh, PA, USA
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Books and Theses
- 2009
[b2]Amith Singhee, Rob A. Rutenbar:
Novel Algorithms for Fast Statistical Analysis of Scaled Circuits. Lecture Notes in Electrical Engineering 46, Springer 2009, ISBN 978-90-481-3099-3, pp. 1-173 [contents]- 1984
- [b1]Rob A. Rutenbar:
A Class of Cellular Computer Architectures to Support Physical Design Automation (Vlsi Layout, Integrated Circuit, Routing). University of Michigan, USA, 1984
Journal Articles
- 2024
- [j42]Sunwoong Kim
, Cameron James Norris, James I. Oelund, Rob A. Rutenbar:
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. IEEE Trans. Very Large Scale Integr. Syst. 32(3): 455-467 (2024) - 2018
- [j41]Francine Berman, Rob A. Rutenbar, Brent Hailpern, Henrik I. Christensen, Susan B. Davidson, Deborah Estrin, Michael J. Franklin, Margaret Martonosi, Padma Raghavan, Victoria Stodden, Alexander S. Szalay:
Realizing the potential of data science. Commun. ACM 61(4): 67-72 (2018) - [j40]Glenn G. Ko, Rob A. Rutenbar:
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field. ACM J. Emerg. Technol. Comput. Syst. 14(2): 17:1-17:22 (2018) - 2016
- [j39]Jungwook Choi, Rob A. Rutenbar:
Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform. IEEE Trans. Circuits Syst. Video Technol. 26(2): 385-398 (2016) - [j38]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 897-908 (2016) - 2014
- [j37]Rob A. Rutenbar:
DAC at 50: The Second 25 Years. IEEE Des. Test 31(2): 32-39 (2014) - 2013
- [j36]Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar:
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(7): 1072-1085 (2013) - 2011
- [j35]Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton:
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1814-1827 (2011) - 2010
- [j34]Amith Singhee, Rob A. Rutenbar:
Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1763-1776 (2010) - [j33]Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun:
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1908-1920 (2010) - 2009
- [j32]Amith Singhee, Rob A. Rutenbar:
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1176-1189 (2009) - 2008
- [j31]Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard:
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96(2): 343-365 (2008) - [j30]Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar:
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2317-2330 (2008) - 2007
- [j29]Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet S. Roychowdhury:
Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. Proc. IEEE 95(3): 640-669 (2007) - [j28]James D. Ma, Rob A. Rutenbar:
Interval-Valued Reduced-Order Statistical Interconnect Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1602-1613 (2007) - 2006
- [j27]James D. Ma, Rob A. Rutenbar:
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 710-724 (2006) - 2004
- [j26]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar:
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004) - 2003
- [j25]Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 814-820 (2003) - 2002
- [j24]Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar:
Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform. EURASIP J. Adv. Signal Process. 2002(9): 879-892 (2002) - [j23]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 674-684 (2002) - 2001
- [j22]Rony Kay, Rob A. Rutenbar:
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 672-679 (2001) - 2000
- [j21]Georges G. E. Gielen, Rob A. Rutenbar:
Computer-aided design of analog and mixed-signal integrated circuits. Proc. IEEE 88(12): 1825-1854 (2000) - [j20]Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(6): 703-717 (2000) - [j19]Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar:
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 825-839 (2000) - [j18]J. Y. F. Tong, David Nagle, Rob A. Rutenbar:
Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 273-286 (2000) - 1999
- [j17]Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley:
Device-level early floorplanning algorithms for RF circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 375-388 (1999) - 1998
- [j16]Sudip Nag, Rob A. Rutenbar:
Performance-driven simultaneous placement and routing for FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 499-518 (1998) - [j15]R. Glenn Wood, Rob A. Rutenbar:
FPGA routing and routability estimation via Boolean satisfiability. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 222-231 (1998) - 1996
- [j14]Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley:
Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 273-294 (1996) - 1995
- [j13]Sujoy Mitra, Rob A. Rutenbar, L. Richard Carley, David J. Allstot:
Substrate-aware mixed-signal macrocell placement in WRIGHT. IEEE J. Solid State Circuits 30(3): 269-278 (1995) - [j12]Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley:
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization. IEEE J. Solid State Circuits 30(3): 321-326 (1995) - [j11]Stephen W. Director, Pradeep K. Khosla, Ronald A. Rohrer, Rob A. Rutenbar:
Reengineering the curriculum: design and analysis of a new undergraduate Electrical and Computer Engineering degree at Carnegie Mellon University. Proc. IEEE 83(9): 1246-1269 (1995) - [j10]Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar:
Integer programming based topology selection of cell-level analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 401-412 (1995) - 1994
- [j9]Balsha R. Stanisic, Nishath K. Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot:
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. IEEE J. Solid State Circuits 29(3): 226-238 (1994) - 1992
- [j8]Dorothy E. Setliff, Rob A. Rutenbar:
Knowledge Representation and Reasoning in a Software Synthesis Architecture. IEEE Trans. Software Eng. 18(6): 523-533 (1992) - 1991
- [j7]Dorothy E. Setliff, Rob A. Rutenbar:
On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 783-801 (1991) - [j6]Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
Massively parallel switch-level simulation: a feasibility study. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7): 871-894 (1991) - 1989
- [j5]Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
OASYS: a framework for analog circuit synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1247-1266 (1989) - 1988
- [j4]Rob A. Rutenbar, Daniel E. Atkins:
Systolic routing hardware: performance evaluation and optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 397-410 (1988) - 1987
- [j3]Saul A. Kravitz, Rob A. Rutenbar:
Placement by Simulated Annealing on a Multiprocessor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(4): 534-549 (1987) - [j2]Erik C. Carlson, Rob A. Rutenbar:
A Scanline Data Structure Processor for VLSI Geometry Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 780-794 (1987) - 1984
- [j1]Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins:
A Class of Cellular Architectures to Support Physical Design Automation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(4): 264-278 (1984)
Conference and Workshop Papers
- 2022
- [c131]Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar:
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. ASAP 2022: 1-10 - 2020
- [c130]Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar:
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. FCCM 2020: 56-64 - [c129]Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar:
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. FPGA 2020: 318 - [c128]Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, Gu-Yeon Wei, David Brooks:
A Scalable Bayesian Inference Accelerator for Unsupervised Learning. Hot Chips Symposium 2020: 1-27 - [c127]Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei:
A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm. VLSI Circuits 2020: 1-2 - 2019
- [c126]Tianqi Gao, Rob A. Rutenbar:
A Virtual Image Accelerator for Graph Cuts Inference on FPGA. ASAP 2019: 137 - [c125]Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei:
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. FCCM 2019: 334 - [c124]Tianqi Gao, Rob A. Rutenbar:
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference. FPGA 2019: 120 - [c123]Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei:
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. FPL 2019: 159-165 - [c122]Sunwoong Kim, Rob A. Rutenbar:
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA. ACM Great Lakes Symposium on VLSI 2019: 87-92 - [c121]Sunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon, Rob A. Rutenbar:
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. ReConFig 2019: 1-8 - 2018
- [c120]Sunwoong Kim, Rob A. Rutenbar:
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. FCCM 2018: 218 - 2017
- [c119]Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar:
Toward a pixel-parallel architecture for graph cuts inference on FPGA. FPL 2017: 1-4 - [c118]Glenn G. Ko, Rob A. Rutenbar:
A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference. ICASSP 2017: 2477-2481 - 2016
- [c117]Jungwook Choi, Rob A. Rutenbar:
Configurable and scalable belief propagation accelerator for computer vision. FPL 2016: 1-4 - [c116]Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag:
Analysis of error resiliency of belief propagation in computer vision. ICASSP 2016: 1060-1064 - [c115]Rob A. Rutenbar:
Keynote address Wednesday: Hardware inference accelerators for machine learning. ITC 2016: 10 - 2015
- [c114]Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar:
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. FPL 2015: 1-8 - [c113]Rob A. Rutenbar:
Analog Circuit and Layout Synthesis Revisited. ISPD 2015: 83 - 2014
- [c112]Abner Guzmán-Rivera, Pushmeet Kohli, Dhruv Batra, Rob A. Rutenbar:
Efficiently Enforcing Diversity in Multi-Output Structured Prediction. AISTATS 2014: 284-292 - [c111]Rob A. Rutenbar:
The First EDA MOOC: Teaching Design Automation to Planet Earth. DAC 2014: 213:1-213:6 - [c110]Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
A robust message passing based stereo matching kernel via system-level error resiliency. ICASSP 2014: 8331-8335 - 2013
- [c109]Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar:
Automatic clustering of wafer spatial signatures. DAC 2013: 71:1-71:6 - [c108]Jungwook Choi, Rob A. Rutenbar:
Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform. FPGA 2013: 63-72 - [c107]Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmán-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen:
EMERALD: Characterization of emerging applications and algorithms for low-power devices. ISPASS 2013: 122-123 - [c106]Jungwook Choi, Rob A. Rutenbar:
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching. MEMOCODE 2013: 139-142 - [c105]Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag:
Error resilient MRF message passing architecture for stereo matching. SiPS 2013: 348-353 - 2012
- [c104]Jeffrey R. Johnston, Rob A. Rutenbar:
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers. ASAP 2012: 77-85 - [c103]Jungwook Choi, Rob A. Rutenbar:
Hardware implementation of MRF map inference on an FPGA platform. FPL 2012: 209-216 - [c102]Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Emrah Acar, Frank Liu, Rob A. Rutenbar:
Spatial variation decomposition via sparse regression. ICICDT 2012: 1-4 - [c101]Minje Kim, Paris Smaragdis, Glenn G. Ko, Rob A. Rutenbar:
Stereophonic spectrogram segmentation using Markov random fields. MLSP 2012: 1-6 - 2011
- [c100]Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar:
Toward efficient spatial variation decomposition via sparse regression. ICCAD 2011: 162-169 - 2010
- [c99]Wangyang Zhang, Xin Li, Rob A. Rutenbar:
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. DAC 2010: 262-267 - [c98]Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar:
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. ICCAD 2010: 47-54 - [c97]Rob A. Rutenbar:
Analog layout synthesis: what's missing? ISPD 2010: 43 - 2009
- [c96]Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen:
Oil fields, hedge funds, and drugs. DAC 2009: 416-417 - [c95]Edward C. Lin, Rob A. Rutenbar:
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. FPGA 2009: 83-92 - [c94]Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton:
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD 2009: 433-440 - [c93]Kai Yu, Rob A. Rutenbar:
Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis. INTERSPEECH 2009: 1923-1926 - 2008
- [c92]Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman:
Verifying really complex systems: on earth and beyond. DAC 2008: 552-553 - [c91]Amith Singhee, Sonia Singhal, Rob A. Rutenbar:
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. DATE 2008: 856-861 - [c90]Amith Singhee, Sonia Singhal, Rob A. Rutenbar:
Practical, fast Monte Carlo statistical static timing analysis: why and how. ICCAD 2008: 190-195 - [c89]Patrick J. Bourke, Rob A. Rutenbar:
A low-power hardware search architecture for speech recognition. INTERSPEECH 2008: 2102-2105 - [c88]Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar:
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. VLSI Design 2008: 131-136 - 2007
- [c87]Rob A. Rutenbar:
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. ASP-DAC 2007 - [c86]Amith Singhee, Rob A. Rutenbar:
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. DAC 2007: 256-261 - [c85]Amith Singhee, Rob A. Rutenbar:
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. DATE 2007: 1379-1384 - [c84]Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun:
Statistical modeling for the minimum standby supply voltage of a full SRAM array. ESSCIRC 2007: 400-403 - [c83]Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen:
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. FPGA 2007: 60-68 - [c82]Kai Yu, Rob A. Rutenbar:
Generating small, accurate acoustic models with a modified Bayesian information criterion. INTERSPEECH 2007: 2109-2112 - [c81]Zhong Xiu, Rob A. Rutenbar:
Mixed-size placement with fixed macrocells using grid-warping. ISPD 2007: 103-110 - [c80]Amith Singhee, Rob A. Rutenbar:
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. ISQED 2007: 685-692 - [c79]Alex K. Jones, Steven P. Levitan, Rob A. Rutenbar, Yuan Xie:
Collaborative VLSI-CAD Instruction in the Digital Sandbox. MSE 2007: 141-142 - 2006
- [c78]Saurabh K. Tiwary, Rob A. Rutenbar:
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. CICC 2006: 185-188 - [c77]Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar:
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. DAC 2006: 31-36 - [c76]Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar:
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. DAC 2006: 167-172 - [c75]Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar:
Verifying analog oscillator circuits using forward/backward abstraction refinement. DATE 2006: 257-262 - [c74]Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen:
In silico vox: Towards speech recognition in silicon. Hot Chips Symposium 2006: 1-27 - [c73]Rob A. Rutenbar:
Design automation for analog: the next generation of tool challenges. ICCAD 2006: 458-460 - [c72]Saurabh K. Tiwary, Rob A. Rutenbar:
Faster, parametric trajectory-based macromodels via localized linear reductions. ICCAD 2006: 876-883 - [c71]Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen:
Moving speech recognition from software to silicon: the in silico vox project. INTERSPEECH 2006 - 2005
- [c70]Saurabh K. Tiwary, Rob A. Rutenbar:
Scalable trajectory methods for on-demand analog macromodel extraction. DAC 2005: 403-408 - [c69]Zhong Xiu, Rob A. Rutenbar:
Timing-driven placement by grid-warping. DAC 2005: 585-591 - [c68]Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee:
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE 2005: 279-280 - [c67]James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning:
Interval-valued statistical modeling of oxide chemical-mechanical polishing. ICCAD 2005: 141-148 - [c66]Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov:
Early research experience with OpenAccess gear: an open source development environment for physical design. ISPD 2005: 94-100 - [c65]James D. Z. Ma, Rob A. Rutenbar:
Fast interval-valued statistical interconnect modeling and reduction. ISPD 2005: 159-166 - [c64]Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler:
Time Domain Verification of Oscillator Circuit Properties. FAC 2005: 9-22 - 2004
- [c63]Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley:
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. DAC 2004: 155-158 - [c62]Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar:
Large-scale placement by grid-warping. DAC 2004: 351-356 - [c61]Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser:
Will Moore's Law rule in the land of analog? DAC 2004: 633 - [c60]Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar:
Towards formal verification of analog designs. ICCAD 2004: 210-217 - [c59]James D. Ma, Rob A. Rutenbar:
Interval-valued reduced order statistical interconnect modeling. ICCAD 2004: 460-467 - [c58]Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu:
Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472 - 2003
- [c57]Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Meng, Reza Rofougaran, James Spoto:
Mixed signals on mixed-signal: the right next technology. DAC 2003: 278-279 - [c56]Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen:
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. DAC 2003: 496-501 - [c55]Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar:
Floating-point error analysis based on affine arithmetic. ICASSP (2) 2003: 561-564 - [c54]Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen:
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. ICCAD 2003: 275-282 - 2002
- [c53]Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley:
Remembrance of circuits past: macromodeling by data mining in large analog design spaces. DAC 2002: 437-442 - [c52]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369 - [c51]Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar:
Floating-point bit-width optimization for low-power signal processing applications. ICASSP 2002: 3208-3211 - [c50]Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. ISPD 2002: 182-187 - 2001
- [c49]Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen:
Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322 - [c48]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565 - [c47]Rob A. Rutenbar:
Synthesis for Industrial-Scale Analog Intellectual Property. Evolvable Hardware 2001: 3-6 - [c46]Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley:
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. ICCAD 2001: 350-357 - [c45]Prakash Gopalakrishnan, Rob A. Rutenbar:
Direct Transistor-Level Layout for Digital Blocks. ICCAD 2001: 577- - [c44]Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen:
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. ICCAD 2001 - [c43]Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni:
Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD 2001: 656 - [c42]Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone:
Low-power technology mapping for mixed-swing logic. ISLPED 2001: 291-294 - [c41]Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar:
A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227 - 2000
- [c40]Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. DAC 2000: 1-6 - [c39]Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow:
Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). DAC 2000: 85 - [c38]Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy:
Survival strategies for mixed-signal systems-on-chip (panel session). DAC 2000: 579-580 - [c37]John M. Cohn, Rob A. Rutenbar, Steve J. Young, Chris Malachowsky, Luis Aldaz:
Case studies: Chip design on the bleeding edge (panel session abstract). DAC 2000: 648 - [c36]Rony Kay, Rob A. Rutenbar:
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. ISPD 2000: 61-68 - [c35]Rob A. Rutenbar, John M. Cohn:
Layout tools for analog ICs and mixed-signal SoCs: a survey. ISPD 2000: 76-83 - 1999
- [c34]Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums:
ANACONDA: robust synthesis of analog circuits via stochastic pattern search. CICC 1999: 567-570 - [c33]Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley:
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. DAC 1999: 945-950 - [c32]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175 - [c31]Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley:
Inverse polarity techniques for high-speed/low-power multipliers. ISLPED 1999: 264-266 - [c30]Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar:
Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577 - 1998
- [c29]Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley:
Device-level early floorplanning algorithms for RF circuits. ISPD 1998: 57-64 - 1997
- [c28]R. Glenn Wood, Rob A. Rutenbar:
FPGA Routing and Routability Estimation via Boolean Satisfiability. FPGA 1997: 119-125 - [c27]Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar:
A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273 - 1996
- [c26]Bulent Basaran, Rob A. Rutenbar:
An O(n) Algorithm for Transistor Stacking with Performance Constraints. DAC 1996: 221-226 - [c25]L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen:
Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. DAC 1996: 298-303 - 1995
- [c24]Sudip K. Nag, Rob A. Rutenbar:
Performance-driven simultaneous place and route for island-style FPGAs. ICCAD 1995: 332-338 - [c23]Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar:
Testability-oriented channel routing. VLSI Design 1995: 208-213 - 1994
- [c22]Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley:
ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. DAC 1994: 24-30 - [c21]Sudip Nag, Rob A. Rutenbar:
Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. DAC 1994: 301-307 - [c20]Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar:
Synthesis of manufacturable analog circuits. ICCAD 1994: 586-593 - 1993
- [c19]Bulent Basaran, Rob A. Rutenbar, L. Richard Carley:
Latchup-aware placement and parasitic-bounded routing of custom analog cells. ICCAD 1993: 415-421 - 1992
- [c18]Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar:
A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. DAC 1992: 698-703 - [c17]Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley:
System-level routing of mixed-signal ASICs in WREN. ICCAD 1992: 394-399 - 1991
- [c16]Rajeev Jayaraman, Rob A. Rutenbar:
A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. ICCAD 1991: 344-347 - [c15]John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley:
Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. ICCAD 1991: 394-397 - 1990
- [c14]Erik C. Carlson, Rob A. Rutenbar:
Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. DAC 1990: 253-259 - 1989
- [c13]Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
Massively Parallel Switch-Level Simulation: A Feasibility Study. DAC 1989: 91-97 - [c12]Dorothy E. Setliff, Rob A. Rutenbar:
ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. DAC 1989: 543-548 - [c11]Rob A. Rutenbar:
Zen and the Art of Analog Design Automation. IFIP Congress 1989: 911 - [c10]Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar:
Logic Simulation on Massively Parallel Architectures. ISCA 1989: 336-343 - 1988
- [c9]Erik C. Carlson, Rob A. Rutenbar:
Mask Verification on the Connection Machine. DAC 1988: 134-140 - [c8]Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
Analog circuit synthesis for performance in OASYS. ICCAD 1988: 492-495 - [c7]David J. Garrod, Rob A. Rutenbar, L. Richard Carley:
Automatic layout of custom analog cells in ANAGRAM. ICCAD 1988: 544-547 - [c6]Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
Analog circuit synthesis and exploration in OASYS. ICCD 1988: 44-47 - 1987
- [c5]Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley:
A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. DAC 1987: 42-49 - 1986
- [c4]Saul A. Kravitz, Rob A. Rutenbar:
Multiprocessor-based placement by simulated annealing. DAC 1986: 567-573 - 1985
- [c3]Rob A. Rutenbar:
Future directions for DA machine research (panel session). DAC 1985: 496-497 - 1982
- [c2]Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins:
Cellular image processing techniques for VLSI circuit layout validation and routing. DAC 1982: 537-543 - 1981
- [c1]Rob A. Rutenbar, Y. E. Park:
Case study of a VLSI design project: A simple inner product machine. IEEE Symposium on Computer Arithmetic 1981: 184-189
Editorship
- 1996
- [e1]Rob A. Rutenbar, Ralph H. J. M. Otten:
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996. IEEE Computer Society / ACM 1996, ISBN 0-8186-7597-7 [contents]
Informal and Other Publications
- 2022
- [i2]Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar:
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. CoRR abs/2201.03558 (2022) - 2007
- [i1]Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee:
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. CoRR abs/0710.4722 (2007)
Coauthor Index
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