BibTeX record conf/fmcad/KhasidashviliKV09

download as .bib file

@inproceedings{DBLP:conf/fmcad/KhasidashviliKV09,
  author       = {Zurab Khasidashvili and
                  Mahmoud Kinanah and
                  Andrei Voronkov},
  title        = {Verifying equivalence of memories using a first order logic theorem
                  prover},
  booktitle    = {Proceedings of 9th International Conference on Formal Methods in Computer-Aided
                  Design, {FMCAD} 2009, 15-18 November 2009, Austin, Texas, {USA}},
  pages        = {128--135},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/FMCAD.2009.5351132},
  doi          = {10.1109/FMCAD.2009.5351132},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/fmcad/KhasidashviliKV09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.