BibTeX record conf/hpca/Weiss95

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@inproceedings{DBLP:conf/hpca/Weiss95,
  author       = {Shlomo Weiss},
  title        = {Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction
                  Queue, Superscalar Processors},
  booktitle    = {Proceedings of the 1st {IEEE} Symposium on High-Performance Computer
                  Architecture {(HPCA} 1995), Raleigh, North Carolina, USA, January
                  22-25, 1995},
  pages        = {14--21},
  publisher    = {{IEEE} Computer Society},
  year         = {1995},
  url          = {https://doi.org/10.1109/HPCA.1995.386559},
  doi          = {10.1109/HPCA.1995.386559},
  timestamp    = {Fri, 24 Mar 2023 00:02:08 +0100},
  biburl       = {https://dblp.org/rec/conf/hpca/Weiss95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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