BibTeX record conf/iscas/ZhangYXMC17

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@inproceedings{DBLP:conf/iscas/ZhangYXMC17,
  author       = {Lei Zhang and
                  Jianxun Yang and
                  Chengbo Xue and
                  Yue Ma and
                  Shan Cao},
  title        = {A two-stage variation-aware task mapping scheme for fault-tolerant
                  multi-core Network-on-Chips},
  booktitle    = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
                  Baltimore, MD, USA, May 28-31, 2017},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/ISCAS.2017.8050632},
  doi          = {10.1109/ISCAS.2017.8050632},
  timestamp    = {Tue, 29 Dec 2020 18:41:09 +0100},
  biburl       = {https://dblp.org/rec/conf/iscas/ZhangYXMC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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