BibTeX record conf/ispass/QianCHYW18

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@inproceedings{DBLP:conf/ispass/QianCHYW18,
  author       = {Cheng Qian and
                  Bruce R. Childers and
                  Libo Huang and
                  Qi Yu and
                  Zhiying Wang},
  title        = {{HMCSP:} Reducing Transaction Latency of CSR-based {SPMV} in Hybrid
                  Memory Cube},
  booktitle    = {{IEEE} International Symposium on Performance Analysis of Systems
                  and Software, {ISPASS} 2018, Belfast, United Kingdom, April 2-4, 2018},
  pages        = {114--116},
  publisher    = {{IEEE} Computer Society},
  year         = {2018},
  url          = {https://doi.org/10.1109/ISPASS.2018.00021},
  doi          = {10.1109/ISPASS.2018.00021},
  timestamp    = {Fri, 24 Mar 2023 00:02:25 +0100},
  biburl       = {https://dblp.org/rec/conf/ispass/QianCHYW18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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