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BibTeX record conf/micro/HuangKEGN16
@inproceedings{DBLP:conf/micro/HuangKEGN16, author = {Cheng{-}Chieh Huang and Rakesh Kumar and Marco Elver and Boris Grot and Vijay Nagarajan}, title = {C\({}^{\mbox{3}}\)D: Mitigating the {NUMA} bottleneck via coherent {DRAM} caches}, booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 2016, Taipei, Taiwan, October 15-19, 2016}, pages = {36:1--36:12}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/MICRO.2016.7783739}, doi = {10.1109/MICRO.2016.7783739}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/HuangKEGN16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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