BibTeX record conf/patmos/SonN04

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@inproceedings{DBLP:conf/patmos/SonN04,
  author    = {Y. S. Son and
               J. W. Na},
  title     = {A New Logic Transformation Method for Both Low Power and High Testability},
  booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
               and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
               Greece, September 15-17, 2004, Proceedings},
  pages     = {770--779},
  year      = {2004},
  crossref  = {DBLP:conf/patmos/2004},
  url       = {https://doi.org/10.1007/978-3-540-30205-6\_79},
  doi       = {10.1007/978-3-540-30205-6\_79},
  timestamp = {Mon, 05 Jun 2017 12:40:45 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/patmos/SonN04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2004,
  editor    = {Enrico Macii and
               Odysseas G. Koufopavlou and
               Vassilis Paliouras},
  title     = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
               and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
               Greece, September 15-17, 2004, Proceedings},
  series    = {Lecture Notes in Computer Science},
  volume    = {3254},
  publisher = {Springer},
  year      = {2004},
  url       = {https://doi.org/10.1007/b100662},
  doi       = {10.1007/b100662},
  isbn      = {3-540-23095-5},
  timestamp = {Mon, 05 Jun 2017 12:40:45 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/patmos/2004},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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