BibTeX record conf/sies/TrillaHAC17

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@inproceedings{DBLP:conf/sies/TrillaHAC17,
  author       = {David Trilla and
                  Carles Hern{\'{a}}ndez and
                  Jaume Abella and
                  Francisco J. Cazorla},
  title        = {Modelling bus contention during system early design stages},
  booktitle    = {12th {IEEE} International Symposium on Industrial Embedded Systems,
                  {SIES} 2017, Toulouse, France, June 14-16, 2017},
  pages        = {1--8},
  publisher    = {{IEEE}},
  year         = {2017},
  url          = {https://doi.org/10.1109/SIES.2017.7993393},
  doi          = {10.1109/SIES.2017.7993393},
  timestamp    = {Fri, 14 Jul 2023 09:14:24 +0200},
  biburl       = {https://dblp.org/rec/conf/sies/TrillaHAC17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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